Lines Matching refs:CondReg
2097 // Selects operate on i1, however, CondReg is 8 bits width and may contain
2102 unsigned CondReg = getRegForValue(Cond);
2103 if (CondReg == 0)
2108 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
2109 unsigned KCondReg = CondReg;
2110 CondReg = createResultReg(&X86::GR32RegClass);
2112 TII.get(TargetOpcode::COPY), CondReg)
2114 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true,
2118 .addReg(CondReg, getKillRegState(CondIsKill))
2320 unsigned CondReg = getRegForValue(Cond);
2321 if (CondReg == 0)
2326 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
2327 unsigned KCondReg = CondReg;
2328 CondReg = createResultReg(&X86::GR32RegClass);
2330 TII.get(TargetOpcode::COPY), CondReg)
2332 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true,
2336 .addReg(CondReg, getKillRegState(CondIsKill))