Lines Matching defs:RetVT
121 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I);
123 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I);
125 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I);
248 MVT RetVT;
252 if (!isTypeLegal(RetTy, RetVT))
255 if (RetVT != MVT::i32 && RetVT != MVT::i64)
2015 bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
2021 if (RetVT < MVT::i16 || RetVT > MVT::i64)
2025 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2147 bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) {
2156 !((Subtarget->hasSSE1() && RetVT == MVT::f32) ||
2157 (Subtarget->hasSSE2() && RetVT == MVT::f64)))
2200 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2209 (RetVT == MVT::f32) ? X86::VCMPSSZrr : X86::VCMPSDZrr;
2222 (RetVT == MVT::f32) ? X86::VMOVSSZrrk : X86::VMOVSDZrrk;
2240 (RetVT == MVT::f32) ? X86::VCMPSSrr : X86::VCMPSDrr;
2242 (RetVT == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr;
2259 switch (RetVT.SimpleTy) {
2282 bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
2286 switch (RetVT.SimpleTy) {
2352 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2361 MVT RetVT;
2362 if (!isTypeLegal(I->getType(), RetVT))
2380 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2391 if (X86FastEmitCMoveSelect(RetVT, I))
2395 if (X86FastEmitSSESelect(RetVT, I))
2400 if (X86FastEmitPseudoSelect(RetVT, I))