Lines Matching refs:State
30 CCState &State) {
41 if (!State.isAllocated(Reg))
53 unsigned Reg = State.AllocateReg(AvailableRegs[I]);
60 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
94 CCState &State) {
98 State.getMachineFunction().getSubtarget())
103 if (!State.isAllocated(Reg)) {
104 unsigned AssigedReg = State.AllocateReg(Reg);
106 State.addLoc(
111 if (Is64bit && State.IsShadowAllocatedReg(Reg)) {
112 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
130 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
135 ArgFlags, State);
147 if (State.isAllocated(X86::R9)) {
149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT));
157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs());
160 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
166 State.getMachineFunction().getSubtarget().getRegisterInfo();
169 State.AllocateStack(8, 8);
172 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
190 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
195 ArgFlags, State);
211 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
212 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
239 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
245 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
261 if (unsigned Reg = State.AllocateReg(RegList)) {
262 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
277 unsigned FirstFree = State.getFirstUnallocated(RegList);
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++]));
284 It.convertToMem(State.AllocateStack(4, 4));
285 State.addLoc(It);
299 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
300 const MachineFunction &MF = State.getMachineFunction();
301 size_t ArgCount = State.getMachineFunction().getFunction().arg_size();
308 Offset = State.AllocateStack(5 * SlotSize, 4);
319 (void)State.AllocateStack(6 * SlotSize, 4);
329 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));