Target/RISCV/RISCVInstrInfo.cpp

1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
13 #include "RISCVInstrInfo.h"
35 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
39 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
88 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
113 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
140 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
164 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
204 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
236 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
304 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
338 unsigned RISCVInstrInfo::insertBranch(
375 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
417 bool RISCVInstrInfo::reverseBranchCondition(
425 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
432 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
453 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
492 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
505 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
562 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
585 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
617 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
623 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
640 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
657 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
668 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(
713 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,
761 void RISCVInstrInfo::buildOutlinedFrame(
787 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(