Lines Matching refs:Intrinsic
1216 auto MakeIntrinsicCall = [&](Intrinsic::ID IID) {
1227 return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_rsqrt_approx_ftz_f
1228 : Intrinsic::nvvm_rsqrt_approx_f);
1230 return MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d);
1235 return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_sqrt_approx_ftz_f
1236 : Intrinsic::nvvm_sqrt_approx_f);
1244 DAG.getConstant(Intrinsic::nvvm_rcp_approx_ftz_d, DL, MVT::i32),
1245 MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d));
2754 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2755 switch (Intrinsic) {
2759 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2761 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2763 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2765 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2767 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2769 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2771 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2773 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2775 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2777 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2779 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2781 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2784 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2786 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2788 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2790 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2792 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2794 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2796 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2798 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2800 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2802 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2804 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2806 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2809 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2811 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2813 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2815 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2817 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2819 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2821 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2823 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2825 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2827 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2829 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2831 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2834 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2836 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2838 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2840 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2842 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2844 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2846 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2848 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2850 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2852 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2854 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2856 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2859 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2861 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2863 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2865 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2867 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2869 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2871 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2873 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2875 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2877 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2879 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2881 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2884 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2886 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2888 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2890 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2892 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2894 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2897 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2899 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2901 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2903 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2905 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2907 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2910 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2912 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2914 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2916 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2918 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2920 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2922 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2924 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2926 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2928 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2930 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2932 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2935 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2937 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2939 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2941 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2943 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2945 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2947 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2949 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2951 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2953 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2955 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2957 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2960 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2962 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2964 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2966 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2968 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2970 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2972 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2974 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2976 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2978 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2980 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2982 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2985 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2987 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2989 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2991 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2993 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2995 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2997 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2999 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3001 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3003 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3005 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3007 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3010 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3012 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3014 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3016 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3018 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3020 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3022 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3024 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3026 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3028 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3030 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3032 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3035 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3037 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3039 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3041 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3043 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3045 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3047 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3049 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3051 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3053 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3055 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3057 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3060 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3062 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3064 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3066 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3068 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3070 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3073 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3075 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3077 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3079 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3081 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3083 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3086 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3088 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3090 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3092 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
3094 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3096 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3098 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3100 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3102 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3104 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3106 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3108 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
3113 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
3114 switch (Intrinsic) {
3117 case Intrinsic::nvvm_suld_1d_i8_clamp:
3119 case Intrinsic::nvvm_suld_1d_i16_clamp:
3121 case Intrinsic::nvvm_suld_1d_i32_clamp:
3123 case Intrinsic::nvvm_suld_1d_i64_clamp:
3125 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3127 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3129 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3131 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3133 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3135 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3137 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3139 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3141 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3143 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3145 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3147 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3149 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3151 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3153 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3155 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3157 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3159 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3161 case Intrinsic::nvvm_suld_2d_i8_clamp:
3163 case Intrinsic::nvvm_suld_2d_i16_clamp:
3165 case Intrinsic::nvvm_suld_2d_i32_clamp:
3167 case Intrinsic::nvvm_suld_2d_i64_clamp:
3169 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3171 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3173 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3175 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3177 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3179 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3181 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3183 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3185 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3187 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3189 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3191 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3193 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3195 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3197 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3199 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3201 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3203 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3205 case Intrinsic::nvvm_suld_3d_i8_clamp:
3207 case Intrinsic::nvvm_suld_3d_i16_clamp:
3209 case Intrinsic::nvvm_suld_3d_i32_clamp:
3211 case Intrinsic::nvvm_suld_3d_i64_clamp:
3213 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3215 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3217 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3219 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3221 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3223 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3225 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3227 case Intrinsic::nvvm_suld_1d_i8_trap:
3229 case Intrinsic::nvvm_suld_1d_i16_trap:
3231 case Intrinsic::nvvm_suld_1d_i32_trap:
3233 case Intrinsic::nvvm_suld_1d_i64_trap:
3235 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3237 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3239 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3241 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3243 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3245 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3247 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3249 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3251 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3253 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3255 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3257 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3259 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3261 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3263 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3265 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3267 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3269 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3271 case Intrinsic::nvvm_suld_2d_i8_trap:
3273 case Intrinsic::nvvm_suld_2d_i16_trap:
3275 case Intrinsic::nvvm_suld_2d_i32_trap:
3277 case Intrinsic::nvvm_suld_2d_i64_trap:
3279 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3281 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3283 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3285 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3287 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3289 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3291 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3293 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3295 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3297 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3299 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3301 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3303 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3305 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3307 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3309 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3311 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3313 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3315 case Intrinsic::nvvm_suld_3d_i8_trap:
3317 case Intrinsic::nvvm_suld_3d_i16_trap:
3319 case Intrinsic::nvvm_suld_3d_i32_trap:
3321 case Intrinsic::nvvm_suld_3d_i64_trap:
3323 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3325 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3327 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3329 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3331 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3333 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3335 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3337 case Intrinsic::nvvm_suld_1d_i8_zero:
3339 case Intrinsic::nvvm_suld_1d_i16_zero:
3341 case Intrinsic::nvvm_suld_1d_i32_zero:
3343 case Intrinsic::nvvm_suld_1d_i64_zero:
3345 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3347 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3349 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3351 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3353 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3355 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3357 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3359 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3361 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3363 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3365 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3367 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3369 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3371 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3373 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3375 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3377 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3379 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3381 case Intrinsic::nvvm_suld_2d_i8_zero:
3383 case Intrinsic::nvvm_suld_2d_i16_zero:
3385 case Intrinsic::nvvm_suld_2d_i32_zero:
3387 case Intrinsic::nvvm_suld_2d_i64_zero:
3389 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3391 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3393 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3395 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3397 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3399 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3401 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3403 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3405 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3407 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3409 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3411 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3413 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3415 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3417 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3419 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3421 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3423 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3425 case Intrinsic::nvvm_suld_3d_i8_zero:
3427 case Intrinsic::nvvm_suld_3d_i16_zero:
3429 case Intrinsic::nvvm_suld_3d_i32_zero:
3431 case Intrinsic::nvvm_suld_3d_i64_zero:
3433 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3435 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3437 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3439 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3441 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3443 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3445 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3457 MachineFunction &MF, unsigned Intrinsic) const {
3458 switch (Intrinsic) {
3461 case Intrinsic::nvvm_match_all_sync_i32p:
3462 case Intrinsic::nvvm_match_all_sync_i64p:
3472 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col:
3473 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row:
3474 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col_stride:
3475 case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row_stride:
3476 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col:
3477 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row:
3478 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col_stride:
3479 case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row_stride:
3480 case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_col:
3481 case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_row:
3482 case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_col_stride:
3483 case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_row_stride:
3484 case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_col:
3485 case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_row:
3486 case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_col_stride:
3487 case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_row_stride:
3488 case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_col:
3489 case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_row:
3490 case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_col_stride:
3491 case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_row_stride:
3492 case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_col:
3493 case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_row:
3494 case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_col_stride:
3495 case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_row_stride: {
3504 case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_col:
3505 case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_col_stride:
3506 case Intrinsic::nvvm_wmma_m16n16k16_load_a_u8_col_stride:
3507 case Intrinsic::nvvm_wmma_m16n16k16_load_a_u8_col:
3508 case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_row:
3509 case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_row_stride:
3510 case Intrinsic::nvvm_wmma_m16n16k16_load_a_u8_row_stride:
3511 case Intrinsic::nvvm_wmma_m16n16k16_load_a_u8_row:
3512 case Intrinsic::nvvm_wmma_m16n16k16_load_b_s8_col:
3513 case Intrinsic::nvvm_wmma_m16n16k16_load_b_s8_col_stride:
3514 case Intrinsic::nvvm_wmma_m16n16k16_load_b_u8_col_stride:
3515 case Intrinsic::nvvm_wmma_m16n16k16_load_b_u8_col:
3516 case Intrinsic::nvvm_wmma_m16n16k16_load_b_s8_row:
3517 case Intrinsic::nvvm_wmma_m16n16k16_load_b_s8_row_stride:
3518 case Intrinsic::nvvm_wmma_m16n16k16_load_b_u8_row_stride:
3519 case Intrinsic::nvvm_wmma_m16n16k16_load_b_u8_row: {
3529 case Intrinsic::nvvm_wmma_m32n8k16_load_a_s8_col:
3530 case Intrinsic::nvvm_wmma_m32n8k16_load_a_s8_col_stride:
3531 case Intrinsic::nvvm_wmma_m32n8k16_load_a_u8_col_stride:
3532 case Intrinsic::nvvm_wmma_m32n8k16_load_a_u8_col:
3533 case Intrinsic::nvvm_wmma_m32n8k16_load_a_s8_row:
3534 case Intrinsic::nvvm_wmma_m32n8k16_load_a_s8_row_stride:
3535 case Intrinsic::nvvm_wmma_m32n8k16_load_a_u8_row_stride:
3536 case Intrinsic::nvvm_wmma_m32n8k16_load_a_u8_row:
3538 case Intrinsic::nvvm_wmma_m8n32k16_load_b_s8_col:
3539 case Intrinsic::nvvm_wmma_m8n32k16_load_b_s8_col_stride:
3540 case Intrinsic::nvvm_wmma_m8n32k16_load_b_u8_col_stride:
3541 case Intrinsic::nvvm_wmma_m8n32k16_load_b_u8_col:
3542 case Intrinsic::nvvm_wmma_m8n32k16_load_b_s8_row:
3543 case Intrinsic::nvvm_wmma_m8n32k16_load_b_s8_row_stride:
3544 case Intrinsic::nvvm_wmma_m8n32k16_load_b_u8_row_stride:
3545 case Intrinsic::nvvm_wmma_m8n32k16_load_b_u8_row: {
3555 case Intrinsic::nvvm_wmma_m32n8k16_load_b_s8_col:
3556 case Intrinsic::nvvm_wmma_m32n8k16_load_b_s8_col_stride:
3557 case Intrinsic::nvvm_wmma_m32n8k16_load_b_u8_col_stride:
3558 case Intrinsic::nvvm_wmma_m32n8k16_load_b_u8_col:
3559 case Intrinsic::nvvm_wmma_m32n8k16_load_b_s8_row:
3560 case Intrinsic::nvvm_wmma_m32n8k16_load_b_s8_row_stride:
3561 case Intrinsic::nvvm_wmma_m32n8k16_load_b_u8_row_stride:
3562 case Intrinsic::nvvm_wmma_m32n8k16_load_b_u8_row:
3564 case Intrinsic::nvvm_wmma_m8n32k16_load_a_s8_col:
3565 case Intrinsic::nvvm_wmma_m8n32k16_load_a_s8_col_stride:
3566 case Intrinsic::nvvm_wmma_m8n32k16_load_a_u8_col_stride:
3567 case Intrinsic::nvvm_wmma_m8n32k16_load_a_u8_col:
3568 case Intrinsic::nvvm_wmma_m8n32k16_load_a_s8_row:
3569 case Intrinsic::nvvm_wmma_m8n32k16_load_a_s8_row_stride:
3570 case Intrinsic::nvvm_wmma_m8n32k16_load_a_u8_row_stride:
3571 case Intrinsic::nvvm_wmma_m8n32k16_load_a_u8_row:
3572 case Intrinsic::nvvm_wmma_m8n8k128_load_a_b1_row:
3573 case Intrinsic::nvvm_wmma_m8n8k128_load_a_b1_row_stride:
3574 case Intrinsic::nvvm_wmma_m8n8k128_load_b_b1_col:
3575 case Intrinsic::nvvm_wmma_m8n8k128_load_b_b1_col_stride:
3576 case Intrinsic::nvvm_wmma_m8n8k32_load_a_s4_row:
3577 case Intrinsic::nvvm_wmma_m8n8k32_load_a_s4_row_stride:
3578 case Intrinsic::nvvm_wmma_m8n8k32_load_a_u4_row_stride:
3579 case Intrinsic::nvvm_wmma_m8n8k32_load_a_u4_row:
3580 case Intrinsic::nvvm_wmma_m8n8k32_load_b_s4_col:
3581 case Intrinsic::nvvm_wmma_m8n8k32_load_b_s4_col_stride:
3582 case Intrinsic::nvvm_wmma_m8n8k32_load_b_u4_col_stride:
3583 case Intrinsic::nvvm_wmma_m8n8k32_load_b_u4_col: {
3593 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col:
3594 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row:
3595 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col_stride:
3596 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row_stride:
3597 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_col:
3598 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_row:
3599 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_col_stride:
3600 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_row_stride:
3601 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_col:
3602 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_row:
3603 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_col_stride:
3604 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_row_stride: {
3614 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col:
3615 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row:
3616 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col_stride:
3617 case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row_stride:
3618 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_col:
3619 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_row:
3620 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_col_stride:
3621 case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_row_stride:
3622 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_col:
3623 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_row:
3624 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_col_stride:
3625 case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_row_stride: {
3635 case Intrinsic::nvvm_wmma_m16n16k16_load_c_s32_col:
3636 case Intrinsic::nvvm_wmma_m16n16k16_load_c_s32_col_stride:
3637 case Intrinsic::nvvm_wmma_m16n16k16_load_c_s32_row:
3638 case Intrinsic::nvvm_wmma_m16n16k16_load_c_s32_row_stride:
3639 case Intrinsic::nvvm_wmma_m32n8k16_load_c_s32_col:
3640 case Intrinsic::nvvm_wmma_m32n8k16_load_c_s32_col_stride:
3641 case Intrinsic::nvvm_wmma_m32n8k16_load_c_s32_row:
3642 case Intrinsic::nvvm_wmma_m32n8k16_load_c_s32_row_stride:
3643 case Intrinsic::nvvm_wmma_m8n32k16_load_c_s32_col:
3644 case Intrinsic::nvvm_wmma_m8n32k16_load_c_s32_col_stride:
3645 case Intrinsic::nvvm_wmma_m8n32k16_load_c_s32_row:
3646 case Intrinsic::nvvm_wmma_m8n32k16_load_c_s32_row_stride: {
3656 case Intrinsic::nvvm_wmma_m8n8k128_load_c_s32_col:
3657 case Intrinsic::nvvm_wmma_m8n8k128_load_c_s32_col_stride:
3658 case Intrinsic::nvvm_wmma_m8n8k128_load_c_s32_row:
3659 case Intrinsic::nvvm_wmma_m8n8k128_load_c_s32_row_stride:
3660 case Intrinsic::nvvm_wmma_m8n8k32_load_c_s32_col:
3661 case Intrinsic::nvvm_wmma_m8n8k32_load_c_s32_col_stride:
3662 case Intrinsic::nvvm_wmma_m8n8k32_load_c_s32_row:
3663 case Intrinsic::nvvm_wmma_m8n8k32_load_c_s32_row_stride: {
3673 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col:
3674 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row:
3675 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col_stride:
3676 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row_stride:
3677 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_col:
3678 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_row:
3679 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_col_stride:
3680 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_row_stride:
3681 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_col:
3682 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_row:
3683 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_col_stride:
3684 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_row_stride: {
3694 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col:
3695 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row:
3696 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col_stride:
3697 case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row_stride:
3698 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_col:
3699 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_row:
3700 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_col_stride:
3701 case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_row_stride:
3702 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_col:
3703 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_row:
3704 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_col_stride:
3705 case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_row_stride: {
3715 case Intrinsic::nvvm_wmma_m16n16k16_store_d_s32_col:
3716 case Intrinsic::nvvm_wmma_m16n16k16_store_d_s32_col_stride:
3717 case Intrinsic::nvvm_wmma_m16n16k16_store_d_s32_row:
3718 case Intrinsic::nvvm_wmma_m16n16k16_store_d_s32_row_stride:
3719 case Intrinsic::nvvm_wmma_m32n8k16_store_d_s32_col:
3720 case Intrinsic::nvvm_wmma_m32n8k16_store_d_s32_col_stride:
3721 case Intrinsic::nvvm_wmma_m32n8k16_store_d_s32_row:
3722 case Intrinsic::nvvm_wmma_m32n8k16_store_d_s32_row_stride:
3723 case Intrinsic::nvvm_wmma_m8n32k16_store_d_s32_col:
3724 case Intrinsic::nvvm_wmma_m8n32k16_store_d_s32_col_stride:
3725 case Intrinsic::nvvm_wmma_m8n32k16_store_d_s32_row:
3726 case Intrinsic::nvvm_wmma_m8n32k16_store_d_s32_row_stride: {
3736 case Intrinsic::nvvm_wmma_m8n8k128_store_d_s32_col:
3737 case Intrinsic::nvvm_wmma_m8n8k128_store_d_s32_col_stride:
3738 case Intrinsic::nvvm_wmma_m8n8k128_store_d_s32_row:
3739 case Intrinsic::nvvm_wmma_m8n8k128_store_d_s32_row_stride:
3740 case Intrinsic::nvvm_wmma_m8n8k32_store_d_s32_col:
3741 case Intrinsic::nvvm_wmma_m8n8k32_store_d_s32_col_stride:
3742 case Intrinsic::nvvm_wmma_m8n8k32_store_d_s32_row:
3743 case Intrinsic::nvvm_wmma_m8n8k32_store_d_s32_row_stride: {
3753 case Intrinsic::nvvm_atomic_load_inc_32:
3754 case Intrinsic::nvvm_atomic_load_dec_32:
3756 case Intrinsic::nvvm_atomic_add_gen_f_cta:
3757 case Intrinsic::nvvm_atomic_add_gen_f_sys:
3758 case Intrinsic::nvvm_atomic_add_gen_i_cta:
3759 case Intrinsic::nvvm_atomic_add_gen_i_sys:
3760 case Intrinsic::nvvm_atomic_and_gen_i_cta:
3761 case Intrinsic::nvvm_atomic_and_gen_i_sys:
3762 case Intrinsic::nvvm_atomic_cas_gen_i_cta:
3763 case Intrinsic::nvvm_atomic_cas_gen_i_sys:
3764 case Intrinsic::nvvm_atomic_dec_gen_i_cta:
3765 case Intrinsic::nvvm_atomic_dec_gen_i_sys:
3766 case Intrinsic::nvvm_atomic_inc_gen_i_cta:
3767 case Intrinsic::nvvm_atomic_inc_gen_i_sys:
3768 case Intrinsic::nvvm_atomic_max_gen_i_cta:
3769 case Intrinsic::nvvm_atomic_max_gen_i_sys:
3770 case Intrinsic::nvvm_atomic_min_gen_i_cta:
3771 case Intrinsic::nvvm_atomic_min_gen_i_sys:
3772 case Intrinsic::nvvm_atomic_or_gen_i_cta:
3773 case Intrinsic::nvvm_atomic_or_gen_i_sys:
3774 case Intrinsic::nvvm_atomic_exch_gen_i_cta:
3775 case Intrinsic::nvvm_atomic_exch_gen_i_sys:
3776 case Intrinsic::nvvm_atomic_xor_gen_i_cta:
3777 case Intrinsic::nvvm_atomic_xor_gen_i_sys: {
3788 case Intrinsic::nvvm_ldu_global_i:
3789 case Intrinsic::nvvm_ldu_global_f:
3790 case Intrinsic::nvvm_ldu_global_p: {
3793 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3795 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3807 case Intrinsic::nvvm_ldg_global_i:
3808 case Intrinsic::nvvm_ldg_global_f:
3809 case Intrinsic::nvvm_ldg_global_p: {
3813 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3815 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3828 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3829 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3830 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3831 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3832 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3833 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3834 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3835 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3836 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3837 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3838 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3839 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3840 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3841 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3842 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3843 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3844 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3845 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3846 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3847 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3848 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3849 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3850 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3851 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3852 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3853 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3854 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3855 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3856 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3857 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3858 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3859 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3860 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3861 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3862 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3863 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3864 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3865 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3866 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3867 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3868 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3869 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3870 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3871 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3872 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3873 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3874 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3875 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3876 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3877 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3878 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3879 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3880 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3881 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3882 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3883 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
3884 Info.opc = getOpcForTextureInstr(Intrinsic);
3892 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3893 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3894 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3895 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3896 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3897 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3898 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3899 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3900 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3901 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3902 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3903 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3904 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3905 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3906 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3907 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3908 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3909 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3910 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3911 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3912 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3913 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3914 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3915 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3916 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3917 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3918 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3919 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3920 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3921 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3922 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3923 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3924 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3925 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3926 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3927 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3928 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3929 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3930 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3931 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3932 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3933 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3934 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3935 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3936 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3937 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3938 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3939 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3940 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3941 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3942 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3943 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3944 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3945 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3946 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3947 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3948 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3949 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3950 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3951 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3952 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3953 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3954 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3955 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3956 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3957 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3958 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3959 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3960 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3961 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3962 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3963 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3964 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3965 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3966 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3967 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3968 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3969 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3970 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3971 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3972 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3973 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3974 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3975 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3976 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3977 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3978 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3979 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3980 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3981 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3982 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3983 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3984 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3985 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3986 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3987 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3988 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3989 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3990 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3991 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3992 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3993 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3994 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3995 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3996 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3997 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3998 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3999 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
4000 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
4001 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
4002 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
4003 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
4004 Info.opc = getOpcForTextureInstr(Intrinsic);
4012 case Intrinsic::nvvm_suld_1d_i8_clamp:
4013 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
4014 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
4015 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
4016 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
4017 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
4018 case Intrinsic::nvvm_suld_2d_i8_clamp:
4019 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
4020 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
4021 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
4022 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
4023 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
4024 case Intrinsic::nvvm_suld_3d_i8_clamp:
4025 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
4026 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
4027 case Intrinsic::nvvm_suld_1d_i8_trap:
4028 case Intrinsic::nvvm_suld_1d_v2i8_trap:
4029 case Intrinsic::nvvm_suld_1d_v4i8_trap:
4030 case Intrinsic::nvvm_suld_1d_array_i8_trap:
4031 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
4032 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
4033 case Intrinsic::nvvm_suld_2d_i8_trap:
4034 case Intrinsic::nvvm_suld_2d_v2i8_trap:
4035 case Intrinsic::nvvm_suld_2d_v4i8_trap:
4036 case Intrinsic::nvvm_suld_2d_array_i8_trap:
4037 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
4038 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
4039 case Intrinsic::nvvm_suld_3d_i8_trap:
4040 case Intrinsic::nvvm_suld_3d_v2i8_trap:
4041 case Intrinsic::nvvm_suld_3d_v4i8_trap:
4042 case Intrinsic::nvvm_suld_1d_i8_zero:
4043 case Intrinsic::nvvm_suld_1d_v2i8_zero:
4044 case Intrinsic::nvvm_suld_1d_v4i8_zero:
4045 case Intrinsic::nvvm_suld_1d_array_i8_zero:
4046 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
4047 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
4048 case Intrinsic::nvvm_suld_2d_i8_zero:
4049 case Intrinsic::nvvm_suld_2d_v2i8_zero:
4050 case Intrinsic::nvvm_suld_2d_v4i8_zero:
4051 case Intrinsic::nvvm_suld_2d_array_i8_zero:
4052 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
4053 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
4054 case Intrinsic::nvvm_suld_3d_i8_zero:
4055 case Intrinsic::nvvm_suld_3d_v2i8_zero:
4056 case Intrinsic::nvvm_suld_3d_v4i8_zero:
4057 Info.opc = getOpcForSurfaceInstr(Intrinsic);
4065 case Intrinsic::nvvm_suld_1d_i16_clamp:
4066 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
4067 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
4068 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
4069 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
4070 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
4071 case Intrinsic::nvvm_suld_2d_i16_clamp:
4072 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
4073 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
4074 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
4075 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
4076 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
4077 case Intrinsic::nvvm_suld_3d_i16_clamp:
4078 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
4079 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
4080 case Intrinsic::nvvm_suld_1d_i16_trap:
4081 case Intrinsic::nvvm_suld_1d_v2i16_trap:
4082 case Intrinsic::nvvm_suld_1d_v4i16_trap:
4083 case Intrinsic::nvvm_suld_1d_array_i16_trap:
4084 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
4085 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
4086 case Intrinsic::nvvm_suld_2d_i16_trap:
4087 case Intrinsic::nvvm_suld_2d_v2i16_trap:
4088 case Intrinsic::nvvm_suld_2d_v4i16_trap:
4089 case Intrinsic::nvvm_suld_2d_array_i16_trap:
4090 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
4091 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
4092 case Intrinsic::nvvm_suld_3d_i16_trap:
4093 case Intrinsic::nvvm_suld_3d_v2i16_trap:
4094 case Intrinsic::nvvm_suld_3d_v4i16_trap:
4095 case Intrinsic::nvvm_suld_1d_i16_zero:
4096 case Intrinsic::nvvm_suld_1d_v2i16_zero:
4097 case Intrinsic::nvvm_suld_1d_v4i16_zero:
4098 case Intrinsic::nvvm_suld_1d_array_i16_zero:
4099 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
4100 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
4101 case Intrinsic::nvvm_suld_2d_i16_zero:
4102 case Intrinsic::nvvm_suld_2d_v2i16_zero:
4103 case Intrinsic::nvvm_suld_2d_v4i16_zero:
4104 case Intrinsic::nvvm_suld_2d_array_i16_zero:
4105 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
4106 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
4107 case Intrinsic::nvvm_suld_3d_i16_zero:
4108 case Intrinsic::nvvm_suld_3d_v2i16_zero:
4109 case Intrinsic::nvvm_suld_3d_v4i16_zero:
4110 Info.opc = getOpcForSurfaceInstr(Intrinsic);
4118 case Intrinsic::nvvm_suld_1d_i32_clamp:
4119 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
4120 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
4121 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
4122 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
4123 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
4124 case Intrinsic::nvvm_suld_2d_i32_clamp:
4125 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
4126 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
4127 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
4128 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
4129 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
4130 case Intrinsic::nvvm_suld_3d_i32_clamp:
4131 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
4132 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
4133 case Intrinsic::nvvm_suld_1d_i32_trap:
4134 case Intrinsic::nvvm_suld_1d_v2i32_trap:
4135 case Intrinsic::nvvm_suld_1d_v4i32_trap:
4136 case Intrinsic::nvvm_suld_1d_array_i32_trap:
4137 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
4138 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
4139 case Intrinsic::nvvm_suld_2d_i32_trap:
4140 case Intrinsic::nvvm_suld_2d_v2i32_trap:
4141 case Intrinsic::nvvm_suld_2d_v4i32_trap:
4142 case Intrinsic::nvvm_suld_2d_array_i32_trap:
4143 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
4144 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
4145 case Intrinsic::nvvm_suld_3d_i32_trap:
4146 case Intrinsic::nvvm_suld_3d_v2i32_trap:
4147 case Intrinsic::nvvm_suld_3d_v4i32_trap:
4148 case Intrinsic::nvvm_suld_1d_i32_zero:
4149 case Intrinsic::nvvm_suld_1d_v2i32_zero:
4150 case Intrinsic::nvvm_suld_1d_v4i32_zero:
4151 case Intrinsic::nvvm_suld_1d_array_i32_zero:
4152 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
4153 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
4154 case Intrinsic::nvvm_suld_2d_i32_zero:
4155 case Intrinsic::nvvm_suld_2d_v2i32_zero:
4156 case Intrinsic::nvvm_suld_2d_v4i32_zero:
4157 case Intrinsic::nvvm_suld_2d_array_i32_zero:
4158 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
4159 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
4160 case Intrinsic::nvvm_suld_3d_i32_zero:
4161 case Intrinsic::nvvm_suld_3d_v2i32_zero:
4162 case Intrinsic::nvvm_suld_3d_v4i32_zero:
4163 Info.opc = getOpcForSurfaceInstr(Intrinsic);
4171 case Intrinsic::nvvm_suld_1d_i64_clamp:
4172 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
4173 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
4174 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
4175 case Intrinsic::nvvm_suld_2d_i64_clamp:
4176 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
4177 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
4178 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
4179 case Intrinsic::nvvm_suld_3d_i64_clamp:
4180 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
4181 case Intrinsic::nvvm_suld_1d_i64_trap:
4182 case Intrinsic::nvvm_suld_1d_v2i64_trap:
4183 case Intrinsic::nvvm_suld_1d_array_i64_trap:
4184 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
4185 case Intrinsic::nvvm_suld_2d_i64_trap:
4186 case Intrinsic::nvvm_suld_2d_v2i64_trap:
4187 case Intrinsic::nvvm_suld_2d_array_i64_trap:
4188 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
4189 case Intrinsic::nvvm_suld_3d_i64_trap:
4190 case Intrinsic::nvvm_suld_3d_v2i64_trap:
4191 case Intrinsic::nvvm_suld_1d_i64_zero:
4192 case Intrinsic::nvvm_suld_1d_v2i64_zero:
4193 case Intrinsic::nvvm_suld_1d_array_i64_zero:
4194 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
4195 case Intrinsic::nvvm_suld_2d_i64_zero:
4196 case Intrinsic::nvvm_suld_2d_v2i64_zero:
4197 case Intrinsic::nvvm_suld_2d_array_i64_zero:
4198 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
4199 case Intrinsic::nvvm_suld_3d_i64_zero:
4200 case Intrinsic::nvvm_suld_3d_v2i64_zero:
4201 Info.opc = getOpcForSurfaceInstr(Intrinsic);
4921 case Intrinsic::nvvm_ldg_global_i:
4922 case Intrinsic::nvvm_ldg_global_f:
4923 case Intrinsic::nvvm_ldg_global_p:
4924 case Intrinsic::nvvm_ldu_global_i:
4925 case Intrinsic::nvvm_ldu_global_f:
4926 case Intrinsic::nvvm_ldu_global_p: {
4955 case Intrinsic::nvvm_ldg_global_i:
4956 case Intrinsic::nvvm_ldg_global_f:
4957 case Intrinsic::nvvm_ldg_global_p:
4960 case Intrinsic::nvvm_ldu_global_i:
4961 case Intrinsic::nvvm_ldu_global_f:
4962 case Intrinsic::nvvm_ldu_global_p:
4972 case Intrinsic::nvvm_ldg_global_i:
4973 case Intrinsic::nvvm_ldg_global_f:
4974 case Intrinsic::nvvm_ldg_global_p:
4977 case Intrinsic::nvvm_ldu_global_i:
4978 case Intrinsic::nvvm_ldu_global_f:
4979 case Intrinsic::nvvm_ldu_global_p: