Lines Matching defs:Outs
161 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
206 // stay in sync with Ins/Outs.
1261 const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
1316 if (!Outs[OIdx].Flags.isByVal()) {
1327 // update the index for Outs
1335 assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
1336 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
1361 unsigned align = Outs[OIdx].Flags.getByValAlign();
1427 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1448 // Args.size() and Outs.size() need not match.
1449 // Outs.size() will be larger
1451 // showing up separately in Outs)
1454 // individually present in Outs.
1455 // So a different index should be used for indexing into Outs/OutVals.
1461 EVT VT = Outs[OIdx].VT;
1464 if (!Outs[OIdx].Flags.isByVal()) {
1523 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
1586 unsigned sz = Outs[OIdx].Flags.getByValSize();
1588 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1589 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1698 std::string Proto = getPrototype(DL, RetTy, Args, Outs, retAlignment, CS);
2663 const SmallVectorImpl<ISD::OutputArg> &Outs,
2700 RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND