Lines Matching refs:Ex
303 bool operator==(const ExtExpr &Ex) const {
304 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;
306 bool operator!=(const ExtExpr &Ex) const {
307 return !operator==(Ex);
309 bool operator<(const ExtExpr &Ex) const {
310 if (Rs != Ex.Rs)
311 return Rs < Ex.Rs;
312 if (S != Ex.S)
313 return S < Ex.S;
314 return !Neg && Ex.Neg;
461 : Ex(E), HRI(I) {}
462 const HCE::ExtExpr &Ex;
468 OS << "## " << (P.Ex.Neg ? "- " : "+ ");
469 if (P.Ex.Rs.Reg != 0)
470 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
473 OS << " << " << P.Ex.S;
1536 const ExtExpr &Ex = ExtI.second;
1539 if (Ex.Rs.isSlot()) {
1540 assert(Ex.S == 0 && "Cannot have a shift of a stack slot");
1541 assert(!Ex.Neg && "Cannot subtract a stack slot");
1544 .add(MachineOperand(Ex.Rs))
1547 assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) && "Expecting virtual register");
1548 if (Ex.trivial()) {
1552 } else if (Ex.S == 0) {
1553 if (Ex.Neg) {
1557 .add(MachineOperand(Ex.Rs));
1561 .add(MachineOperand(Ex.Rs))
1565 unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri
1570 .add(MachineOperand(Ex.Rs))
1571 .addImm(Ex.S);
1752 const ExtExpr &Ex = ExtI.second; (void)Ex;
1762 assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
1785 assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg && "Initializer mismatch");