Lines Matching defs:SRA
192 setOperationAction(ISD::SRA, VT, Custom);
263 setOperationAction(ISD::SRA, VT, Custom);
920 setTargetDAGCombine(ISD::SRA);
1073 setOperationAction(ISD::SRA, MVT::i64, Custom);
1078 // assuming that ISD::SRL and SRA of i64 are already marked custom
1806 if (Op.getOpcode() != ISD::SRA)
1821 // Check for a signed 16-bit value. We special case SRA because it makes it
3672 SDValue SRA =
3673 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3674 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3695 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4455 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4943 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5856 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5874 SDValue HiBigShift = Opc == ISD::SRA
6110 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6115 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
6126 (N->getOpcode() == ISD::SRA ? ARMISD::VSHLs : ARMISD::VSHLu);
6139 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6168 } else if (ShOpc == ISD::SRA)
6186 // We only lower SRA, SRL of 1 here, all others use generic lowering.
6194 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
9323 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
9434 case ISD::SRA:
11297 // be sign extended somehow or SRA'd into 32-bit values
11308 SDValue SRA = AddeNode->getOperand(0);
11310 if (SRA.getOpcode() != ISD::SRA) {
11311 SRA = AddeNode->getOperand(1);
11313 if (SRA.getOpcode() != ISD::SRA)
11316 if (auto Const = dyn_cast<ConstantSDNode>(SRA.getOperand(1))) {
11322 if (SRA.getOperand(0) != Mul)
12258 // For SMULWT only the SRA is required.
14013 case ISD::SRA:
14017 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
14651 case ISD::SRA:
16485 Tmp = DAG.getNode(ISD::SRA, dl, HalfT, Hi,