Lines Matching defs:NextReg
1236 unsigned NextReg = ARM::D8;
1241 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1247 .addReg(NextReg)
1250 NextReg += 4;
1256 unsigned R4BaseReg = NextReg;
1260 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1266 .addReg(NextReg)
1269 NextReg += 4;
1275 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1283 NextReg += 2;
1289 MBB.addLiveIn(NextReg);
1292 .addReg(NextReg)
1294 .addImm((NextReg - R4BaseReg) * 2)
1369 unsigned NextReg = ARM::D8;
1373 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1375 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1381 NextReg += 4;
1387 unsigned R4BaseReg = NextReg;
1391 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1393 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1398 NextReg += 4;
1404 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1410 NextReg += 2;
1416 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1418 .addImm(2 * (NextReg - R4BaseReg))