Lines Matching refs:Vec
4785 SDValue Vec = Op.getOperand(0);
4788 EVT VecVT = Vec.getValueType();
4798 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
4801 return Vec;
4806 SDValue Vec = Op.getOperand(0);
4809 EVT VecVT = Vec.getValueType();
4822 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
4867 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4885 SDValue Vec = Op.getOperand(0);
4887 EVT VecVT = Vec.getValueType();
4910 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
8552 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
8554 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
9280 SDValue Vec = N->getOperand(0);
9283 EVT VecVT = Vec.getValueType();
9286 if ((Vec.getOpcode() == ISD::FNEG ||
9287 Vec.getOpcode() == ISD::FABS) && allUsesHaveSourceMods(N)) {
9292 Vec.getOperand(0), Idx);
9293 return DAG.getNode(Vec.getOpcode(), SL, EltVT, Elt);
9301 if (Vec.hasOneUse() && DCI.isBeforeLegalize()) {
9305 unsigned Opc = Vec.getOpcode();
9324 Vec.getOperand(0), Idx);
9326 Vec.getOperand(1), Idx);
9330 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags());
9351 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC);
9367 if (isa<MemSDNode>(Vec) &&
9380 SDValue Cast = DAG.getNode(ISD::BITCAST, SL, NewVT, Vec);
9401 SDValue Vec = N->getOperand(0);
9403 EVT VecVT = Vec.getValueType();
9426 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC);