Lines Matching refs:i32
60 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
72 setOperationAction(ISD::LOAD, MVT::i32, Custom);
102 setOperationAction(ISD::STORE, MVT::i32, Custom);
106 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
107 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
139 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
140 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
141 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
142 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
150 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
162 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
164 setOperationAction(ISD::SETCC, MVT::i32, Expand);
171 setOperationAction(ISD::SELECT, MVT::i32, Expand);
179 setOperationAction(ISD::UADDO, MVT::i32, Custom);
182 setOperationAction(ISD::USUBO, MVT::i32, Custom);
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
207 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
219 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
221 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
222 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
223 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
240 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
249 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
256 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
258 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
268 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
269 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
514 DAG.getConstant(0, DL, MVT::i32), // SWZ_X
515 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
516 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
517 DAG.getConstant(3, DL, MVT::i32) // SWZ_W
549 DAG.getConstant(TextureOp, DL, MVT::i32),
551 DAG.getConstant(0, DL, MVT::i32),
552 DAG.getConstant(1, DL, MVT::i32),
553 DAG.getConstant(2, DL, MVT::i32),
554 DAG.getConstant(3, DL, MVT::i32),
558 DAG.getConstant(0, DL, MVT::i32),
559 DAG.getConstant(1, DL, MVT::i32),
560 DAG.getConstant(2, DL, MVT::i32),
561 DAG.getConstant(3, DL, MVT::i32),
574 DAG.getConstant(0, DL, MVT::i32)),
576 DAG.getConstant(0, DL, MVT::i32)),
578 DAG.getConstant(1, DL, MVT::i32)),
580 DAG.getConstant(1, DL, MVT::i32)),
582 DAG.getConstant(2, DL, MVT::i32)),
584 DAG.getConstant(2, DL, MVT::i32)),
586 DAG.getConstant(3, DL, MVT::i32)),
588 DAG.getConstant(3, DL, MVT::i32))
914 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR
971 // select_cc i32, i32, -1, 0, cc_supported
992 (CompareVT == VT || VT == MVT::i32)) {
1002 // select_cc f32, 0.0, i32, i32, cc_supported
1003 // select_cc i32, 0, f32, f32, cc_supported
1004 // select_cc i32, 0, i32, i32, cc_supported
1065 } else if (CompareVT == MVT::i32) {
1107 DAG.getConstant(SRLPad, DL, MVT::i32));
1150 Mask = DAG.getConstant(0xff, DL, MVT::i32);
1153 Mask = DAG.getConstant(0xffff, DL, MVT::i32);
1168 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1173 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1174 DAG.getConstant(0xfffffffc, DL, MVT::i32));
1179 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1184 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1185 DAG.getConstant(0x3, DL, MVT::i32));
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1189 DAG.getConstant(3, DL, MVT::i32));
1192 // it also handles sub i32 non-truncating stores (like i1)
1193 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt);
1208 DstMask = DAG.getNOT(DL, DstMask, MVT::i32);
1211 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1214 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1277 assert(VT.bitsLE(MVT::i32));
1280 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
1284 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
1299 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1303 DAG.getConstant(0, DL, MVT::i32),
1304 DAG.getConstant(0, DL, MVT::i32),
1312 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) {
1329 if (MemVT.bitsLT(MVT::i32))
1332 // Standard i32+ store, tag it with DWORDADDR to note that the address
1339 // Tagged i32+ stores will be matched by patterns
1398 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1403 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1404 DAG.getConstant(0xfffffffc, DL, MVT::i32));
1409 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1412 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1413 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32));
1416 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1417 DAG.getConstant(3, DL, MVT::i32));
1420 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt);
1427 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1447 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
1477 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1478 DAG.getConstant(4, DL, MVT::i32)),
1480 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32)
1485 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1486 DAG.getConstant(0, DL, MVT::i32));
1521 assert(VT == MVT::i32);
1522 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32));
1523 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr);
1524 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand());
1611 // i64 isn't a legal type, so the register type used ends up as i32, which
1637 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32),
1651 return MVT::i32;
1657 // Local and Private addresses do not handle vectors. Limit to i32
1673 if (VT.bitsLT(MVT::i32))
1680 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
1778 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1786 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1801 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode))
1817 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32));
1818 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1828 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1829 DAG.getConstant(0, DL, MVT::i32));
1858 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1859 // (i32 select_cc f32, f32, -1, 0 cc)
1880 DAG.getConstant(-1, DL, MVT::i32), // True
1881 DAG.getConstant(0, DL, MVT::i32), // False
2082 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2088 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2149 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32);
2190 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32);
2192 Src = DAG.getRegister(ImmReg, MVT::i32);