Lines Matching defs:SRA
897 setOperationAction(ISD::SRA, VT, Custom);
2061 if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA)
2263 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
2291 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
3229 case ISD::SRA:
5889 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5924 Opc == ISD::SRA
8349 case ISD::SRA:
8354 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
8362 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
9659 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
9663 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
9722 SDValue SRA =
9723 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
9728 return SRA;
9730 Created.push_back(SRA.getNode());
9731 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
12061 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
12132 case ISD::SRA: