Lines Matching defs:RetVT
196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
201 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
226 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
235 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
239 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
242 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
244 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
248 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
250 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
252 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
255 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
256 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
258 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
260 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
262 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
266 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
270 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
284 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
1160 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
1165 switch (RetVT.SimpleTy) {
1183 MVT SrcVT = RetVT;
1184 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
1210 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1216 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1219 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1223 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,
1239 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1247 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1267 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1292 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1308 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1310 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1314 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1324 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1333 bool Is64Bit = RetVT == MVT::i64;
1352 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1357 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1375 bool Is64Bit = RetVT == MVT::i64;
1397 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1407 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1411 if (ShiftImm >= RetVT.getSizeInBits())
1420 bool Is64Bit = RetVT == MVT::i64;
1440 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1450 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1462 bool Is64Bit = RetVT == MVT::i64;
1507 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1509 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1513 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1515 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,
1519 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1520 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1536 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1547 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1554 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1556 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1584 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1586 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1590 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1593 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1597 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1602 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1607 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1632 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1654 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1670 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1682 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1684 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1685 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1691 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1704 switch (RetVT.SimpleTy) {
1730 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1731 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1737 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1750 if (ShiftImm >= RetVT.getSizeInBits())
1755 switch (RetVT.SimpleTy) {
1773 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1774 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1780 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1782 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
1785 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1861 bool IsRet64Bit = RetVT == MVT::i64;
1910 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
2008 MVT RetVT = VT;
2012 if (isTypeSupported(ZE->getType(), RetVT))
2015 RetVT = VT;
2017 if (isTypeSupported(SE->getType(), RetVT))
2020 RetVT = VT;
2026 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
2049 if (RetVT == MVT::i64 && VT <= MVT::i32) {
3152 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
3162 if (RetVT != MVT::isVoid) {
3165 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
3224 MVT RetVT;
3226 RetVT = MVT::isVoid;
3227 else if (!isTypeLegal(CLI.RetTy, RetVT))
3324 return finishCall(CLI, RetVT, NumBytes);
3399 MVT RetVT;
3403 if (!isTypeLegal(RetTy, RetVT))
3406 if (RetVT != MVT::i32 && RetVT != MVT::i64)
3578 MVT RetVT;
3579 if (!isTypeLegal(II->getType(), RetVT))
3582 if (RetVT != MVT::f32 && RetVT != MVT::f64)
3591 bool Is64Bit = RetVT == MVT::f64;
4046 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
4049 switch (RetVT.SimpleTy) {
4054 RetVT = MVT::i32;
4061 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4066 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
4068 if (RetVT != MVT::i64)
4076 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
4078 if (RetVT != MVT::i64)
4086 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4091 switch (RetVT.SimpleTy) {
4100 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4112 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4115 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4120 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4121 RetVT == MVT::i64) && "Unexpected return value type.");
4123 bool Is64Bit = (RetVT == MVT::i64);
4125 unsigned DstBits = RetVT.getSizeInBits();
4132 if (RetVT == SrcVT) {
4139 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4179 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4192 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4197 switch (RetVT.SimpleTy) {
4206 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4219 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4222 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4227 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4228 RetVT == MVT::i64) && "Unexpected return value type.");
4230 bool Is64Bit = (RetVT == MVT::i64);
4232 unsigned DstBits = RetVT.getSizeInBits();
4239 if (RetVT == SrcVT) {
4246 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4279 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4284 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4288 SrcVT = RetVT;
4300 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4313 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4318 switch (RetVT.SimpleTy) {
4327 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4329 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false);
4340 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4343 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4348 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4349 RetVT == MVT::i64) && "Unexpected return value type.");
4351 bool Is64Bit = (RetVT == MVT::i64);
4353 unsigned DstBits = RetVT.getSizeInBits();
4360 if (RetVT == SrcVT) {
4367 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4400 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4409 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4531 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
4560 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4588 MVT RetVT;
4590 if (!isTypeSupported(I->getType(), RetVT))
4597 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4609 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4631 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4759 MVT RetVT;
4760 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
4763 if (RetVT.isVector())
4769 MVT SrcVT = RetVT;
4800 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4803 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4806 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4830 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4833 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4836 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4848 MVT RetVT, SrcVT;
4852 if (!isTypeLegal(I->getType(), RetVT))
4856 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4858 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4860 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4862 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4868 switch (RetVT.SimpleTy) {
4889 MVT RetVT;
4890 if (!isTypeLegal(I->getType(), RetVT))
4894 switch (RetVT.SimpleTy) {