Lines Matching refs:DemandedElts
601 APInt DemandedElts = VT.isVector()
604 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth,
611 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
622 if (DemandedBits == 0 || DemandedElts == 0)
625 unsigned NumElts = DemandedElts.getBitWidth();
637 Src, DemandedBits, DemandedElts, DAG, Depth + 1))
653 if (DemandedElts[j])
671 if (DemandedElts[i]) {
685 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
686 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
698 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
699 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
711 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
712 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
756 !DemandedElts[CIdx->getZExtValue()])
768 if (M < 0 || !DemandedElts[i])
786 Op, DemandedBits, DemandedElts, DAG, Depth))
814 APInt DemandedElts = OriginalDemandedElts;
838 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
844 DemandedElts = APInt::getAllOnesValue(NumElts);
858 if (!DemandedElts[0])
873 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
878 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
891 APInt DemandedVecElts(DemandedElts);
897 if (!DemandedElts[Idx])
929 APInt BaseElts = DemandedElts;
935 SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
969 SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
983 DemandedElts.extractBits(NumSubElts, i * NumSubElts);
1002 if (!DemandedElts[i])
1064 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
1087 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1091 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
1097 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1099 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1101 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1136 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1140 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
1146 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1148 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1150 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1182 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1186 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO,
1192 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1194 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1196 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1324 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1340 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
1358 if (SimplifyDemandedBits(Op0, DemandedBits.lshr(ShAmt), DemandedElts,
1421 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1444 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
1465 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1487 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1508 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1546 if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) {
1552 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
1562 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
1565 if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO,
1581 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
1591 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
1689 if (IsVecInReg && DemandedElts == 1 &&
1701 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1722 if (IsVecInReg && DemandedElts == 1 &&
1734 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1768 if (IsVecInReg && DemandedElts == 1 &&
1774 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1796 Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1))
1936 if (DemandedElts[j])
1957 if (DemandedElts[i]) {
1979 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1993 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO,
1995 SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO,
2012 if (!LoMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
2014 Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1);
2016 Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1);
2050 if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts,
2057 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
2083 const APInt &DemandedElts,
2092 SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
2154 APInt DemandedElts = OriginalDemandedElts;
2155 unsigned NumElts = DemandedElts.getBitWidth();
2170 DemandedElts.setAllBits();
2173 if (DemandedElts == 0) {
2187 if (!DemandedElts[0]) {
2206 return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef,
2217 if (DemandedElts[i])
2231 if (DemandedElts[i]) {
2259 if (DemandedElts[i])
2269 if (DemandedElts[i]) {
2281 if (!DemandedElts.isAllOnesValue()) {
2288 if (!DemandedElts[i] && !Ops[i].isUndef()) {
2315 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
2336 APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
2341 APInt BaseElts = DemandedElts;
2366 APInt SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
2385 if (!DemandedElts[Idx])
2388 APInt DemandedVecElts(DemandedElts);
2405 if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
2419 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef,
2424 APInt DemandedLHS(DemandedElts);
2425 APInt DemandedRHS(DemandedElts);
2447 if (M < 0 || !DemandedElts[i])
2474 if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) ||
2518 APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts);
2534 if (DemandedElts.isSubsetOf(KnownUndef))
2553 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS,
2557 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS,
2571 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS,
2575 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS,
2586 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef,
2589 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
2605 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
2611 if (DemandedElts.isSubsetOf(KnownUndef))
2618 if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
2635 if (DemandedElts.isSubsetOf(KnownUndef))
2645 const APInt &DemandedElts,
2659 const APInt &DemandedElts, const MachineRegisterInfo &MRI,
2666 const APInt &DemandedElts,
2693 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
2705 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
2713 computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
2718 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,