Lines Matching refs:LaneMask
148 /// A LaneMask to remember on which subregister live ranges we need to call
239 /// LaneMask are split as necessary. @p LaneMask are the lanes that
243 LaneBitmask LaneMask, CoalescerPair &CP,
249 LaneBitmask LaneMask, const CoalescerPair &CP);
967 MaskA |= SA.LaneMask;
970 Allocator, SA.LaneMask,
987 if ((SB.LaneMask & MaskA).any())
1386 SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
1421 MaxMask &= ~SR.LaneMask;
1443 if ((SR.LaneMask & DstMask).none()) {
1446 << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n");
1565 if ((SR.LaneMask & SrcMask).none())
1604 if ((SR.LaneMask & DstMask).none())
1626 if ((SR.LaneMask & UseMask).none())
1661 if ((S.LaneMask & Mask).none())
1971 if ((S.LaneMask & ShrinkMask).none())
1973 LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask)
2210 /// The LaneMask that this liverange will occupy the coalesced register. May
2212 const LaneBitmask LaneMask;
2373 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask,
2377 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
2472 LaneBitmask SMask = TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
2473 if ((SMask & LaneMask).none())
3089 LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
3109 << PrintLaneMask(S.LaneMask) << " at " << Def
3111 ShrinkMask |= S.LaneMask;
3251 LaneBitmask LaneMask,
3254 JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask,
3256 JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask,
3294 LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask)
3315 LaneBitmask LaneMask,
3320 Allocator, LaneMask,
3327 joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);
3384 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
3385 R.LaneMask = Mask;
3400 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
3919 assert((S.LaneMask & ~MaxMask).none());