Lines Matching refs:Hint0
662 void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint0) {
671 << " with hint " << printReg(Hint0, TRI) << '\n');
674 if (Hint0.isPhysical() && MRI->isAllocatable(Hint0) &&
675 RC.contains(Hint0)) {
677 unsigned Cost = calcSpillCost(Hint0);
679 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
682 definePhysReg(MI, Hint0, regFree);
683 assignVirtToPhysReg(LR, Hint0);
686 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
690 Hint0 = Register();
727 if (PhysReg == Hint1 || PhysReg == Hint0)