Lines Matching refs:FALSE

37     { "int32_to_float32",                1, FALSE, TRUE  },
38 { "int32_to_float64", 1, FALSE, FALSE },
39 { "int32_to_floatx80", 1, FALSE, FALSE },
40 { "int32_to_float128", 1, FALSE, FALSE },
41 { "int64_to_float32", 1, FALSE, TRUE },
42 { "int64_to_float64", 1, FALSE, TRUE },
43 { "int64_to_floatx80", 1, FALSE, FALSE },
44 { "int64_to_float128", 1, FALSE, FALSE },
45 { "float32_to_int32", 1, FALSE, TRUE },
46 { "float32_to_int32_round_to_zero", 1, FALSE, FALSE },
47 { "float32_to_int64", 1, FALSE, TRUE },
48 { "float32_to_int64_round_to_zero", 1, FALSE, FALSE },
49 { "float32_to_float64", 1, FALSE, FALSE },
50 { "float32_to_floatx80", 1, FALSE, FALSE },
51 { "float32_to_float128", 1, FALSE, FALSE },
52 { "float32_round_to_int", 1, FALSE, TRUE },
53 { "float32_add", 2, FALSE, TRUE },
54 { "float32_sub", 2, FALSE, TRUE },
55 { "float32_mul", 2, FALSE, TRUE },
56 { "float32_div", 2, FALSE, TRUE },
57 { "float32_rem", 2, FALSE, FALSE },
58 { "float32_sqrt", 1, FALSE, TRUE },
59 { "float32_eq", 2, FALSE, FALSE },
60 { "float32_le", 2, FALSE, FALSE },
61 { "float32_lt", 2, FALSE, FALSE },
62 { "float32_eq_signaling", 2, FALSE, FALSE },
63 { "float32_le_quiet", 2, FALSE, FALSE },
64 { "float32_lt_quiet", 2, FALSE, FALSE },
65 { "float64_to_int32", 1, FALSE, TRUE },
66 { "float64_to_int32_round_to_zero", 1, FALSE, FALSE },
67 { "float64_to_int64", 1, FALSE, TRUE },
68 { "float64_to_int64_round_to_zero", 1, FALSE, FALSE },
69 { "float64_to_float32", 1, FALSE, TRUE },
70 { "float64_to_floatx80", 1, FALSE, FALSE },
71 { "float64_to_float128", 1, FALSE, FALSE },
72 { "float64_round_to_int", 1, FALSE, TRUE },
73 { "float64_add", 2, FALSE, TRUE },
74 { "float64_sub", 2, FALSE, TRUE },
75 { "float64_mul", 2, FALSE, TRUE },
76 { "float64_div", 2, FALSE, TRUE },
77 { "float64_rem", 2, FALSE, FALSE },
78 { "float64_sqrt", 1, FALSE, TRUE },
79 { "float64_eq", 2, FALSE, FALSE },
80 { "float64_le", 2, FALSE, FALSE },
81 { "float64_lt", 2, FALSE, FALSE },
82 { "float64_eq_signaling", 2, FALSE, FALSE },
83 { "float64_le_quiet", 2, FALSE, FALSE },
84 { "float64_lt_quiet", 2, FALSE, FALSE },
85 { "floatx80_to_int32", 1, FALSE, TRUE },
86 { "floatx80_to_int32_round_to_zero", 1, FALSE, FALSE },
87 { "floatx80_to_int64", 1, FALSE, TRUE },
88 { "floatx80_to_int64_round_to_zero", 1, FALSE, FALSE },
89 { "floatx80_to_float32", 1, FALSE, TRUE },
90 { "floatx80_to_float64", 1, FALSE, TRUE },
91 { "floatx80_to_float128", 1, FALSE, FALSE },
92 { "floatx80_round_to_int", 1, FALSE, TRUE },
97 { "floatx80_rem", 2, FALSE, FALSE },
99 { "floatx80_eq", 2, FALSE, FALSE },
100 { "floatx80_le", 2, FALSE, FALSE },
101 { "floatx80_lt", 2, FALSE, FALSE },
102 { "floatx80_eq_signaling", 2, FALSE, FALSE },
103 { "floatx80_le_quiet", 2, FALSE, FALSE },
104 { "floatx80_lt_quiet", 2, FALSE, FALSE },
105 { "float128_to_int32", 1, FALSE, TRUE },
106 { "float128_to_int32_round_to_zero", 1, FALSE, FALSE },
107 { "float128_to_int64", 1, FALSE, TRUE },
108 { "float128_to_int64_round_to_zero", 1, FALSE, FALSE },
109 { "float128_to_float32", 1, FALSE, TRUE },
110 { "float128_to_float64", 1, FALSE, TRUE },
111 { "float128_to_floatx80", 1, FALSE, TRUE },
112 { "float128_round_to_int", 1, FALSE, TRUE },
113 { "float128_add", 2, FALSE, TRUE },
114 { "float128_sub", 2, FALSE, TRUE },
115 { "float128_mul", 2, FALSE, TRUE },
116 { "float128_div", 2, FALSE, TRUE },
117 { "float128_rem", 2, FALSE, FALSE },
118 { "float128_sqrt", 1, FALSE, TRUE },
119 { "float128_eq", 2, FALSE, FALSE },
120 { "float128_le", 2, FALSE, FALSE },
121 { "float128_lt", 2, FALSE, FALSE },
122 { "float128_eq_signaling", 2, FALSE, FALSE },
123 { "float128_le_quiet", 2, FALSE, FALSE },
124 { "float128_lt_quiet", 2, FALSE, FALSE },