Lines Matching refs:MLX4_CMD_TIME_CLASS_A
176 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
339 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
572 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
882 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1096 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1135 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1236 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1301 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1646 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1656 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1712 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1717 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1781 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1798 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1816 MLX4_CMD_DIAG_RPRT, MLX4_CMD_TIME_CLASS_A,
1851 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1861 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1903 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1944 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,