mips/rmi/board.c

72 	struct xlr_gmac_block_t *blk0, *blk1, *blk2;
76 	blk0 = &board->gmac_block[0];
94 			blk0->gmac_port[3].valid = 0;
95 			blk0->num_ports--;
114 			blk0->gmac_port[3].valid = 0;
115 			blk0->num_ports--;
139 			blk0->gmac_port[3].valid = 0;
140 			blk0->num_ports--;
208 	struct xlr_gmac_block_t *blk0, *blk1;
211 	blk0 = &board->gmac_block[0];
224 		blk0->gmac_port[3].valid = 0;
225 		blk0->num_ports--;
237 	struct xlr_gmac_block_t *blk0, *blk1;
241 	blk0 = &board->gmac_block[0];
246 		blk0->mode = XLR_PORT0_RGMII;
247 		blk0->gmac_port[0].type = XLR_RGMII;
248 		blk0->gmac_port[0].phy_addr = 0;
249 		blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET;
266 		blk0->gmac_port[0].mdint_id = 1;
313 				memset(&blk0->gmac_port[i], 0,
314 				    sizeof(blk0->gmac_port[i]));
317 			blk0->type 		= XLR_XGMAC;
318 			blk0->mode 		= XLR_XAUI;
319 			blk0->num_ports 	= 1;
320 			blk0->gmac_port[0].type = XLR_XAUI;
322 			blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase;
328 			blk0->num_ports 	= 1;  /* only 1 RGMII port */
329 			blk0->mode = XLR_PORT0_RGMII;
330 			blk0->gmac_port[0].type = XLR_RGMII;
331 			blk0->gmac_port[0].phy_addr = 0;
332 			blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET;
370 	struct xlr_gmac_block_t *blk0, *blk1, *blk2;
423 	blk0 = &xlr_board_info.gmac_block[0];
449 		blk0->type 		= XLR_GMAC;
450 		blk0->enabled 		= 0xf;
451 		blk0->credit_config 	= &xls_cc_table_gmac0;
452 		blk0->station_id 	= MSGRNG_STNID_GMAC;
453 		blk0->station_txbase 	= MSGRNG_STNID_GMACTX0;
454 		blk0->station_rfr 	= MSGRNG_STNID_GMACRFR_0;
455 		blk0->mode 		= XLR_SGMII;
456 		blk0->baseaddr 		= XLR_IO_GMAC_0_OFFSET;
457 		blk0->baseirq 		= PIC_GMAC_0_IRQ;
458 		blk0->baseinst 		= 0;
463 			blk0->gmac_port[i].valid = 1;
464 			blk0->gmac_port[i].instance = i + blk0->baseinst;
465 			blk0->gmac_port[i].type = XLR_SGMII;
466 			blk0->gmac_port[i].phy_addr = i + 16;
467 			blk0->gmac_port[i].tx_bucket_id =
468 			    blk0->station_txbase + i;
469 			blk0->gmac_port[i].mdint_id = 0;
470 			blk0->num_ports++;
471 			blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
472 			blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
473 			blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET;
474 			blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
521 		blk0->type 		= XLR_GMAC;
522 		blk0->enabled 		= 0xf;
523 		blk0->credit_config 	= &cc_table_gmac;
524 		blk0->station_id 	= MSGRNG_STNID_GMAC;
525 		blk0->station_txbase 	= MSGRNG_STNID_GMACTX0;
526 		blk0->station_rfr 	= MSGRNG_STNID_GMACRFR_0;
527 		blk0->mode 		= XLR_RGMII;
528 		blk0->baseaddr 		= XLR_IO_GMAC_0_OFFSET;
529 		blk0->baseirq 		= PIC_GMAC_0_IRQ;
530 		blk0->baseinst 		= 0;
534 			blk0->gmac_port[i].valid = 1;
535 			blk0->gmac_port[i].instance = i + blk0->baseinst;
536 			blk0->gmac_port[i].type = XLR_RGMII;
537 			blk0->gmac_port[i].phy_addr = i;
538 			blk0->gmac_port[i].tx_bucket_id =
539 			    blk0->station_txbase + i;
540 			blk0->gmac_port[i].mdint_id = 0;
541 			blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
542 			blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
544 			blk0->num_ports++;