Lines Matching defs:nae_base
47 nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks)
53 nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, fifo_mask);
55 data = nlm_read_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP);
58 nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, 0);
62 nlm_program_nae_parser_seq_fifo(uint64_t nae_base, int maxports,
73 nlm_write_nae_reg(nae_base, NAE_PARSER_SEQ_FIFO_CFG, val);
79 nlm_setup_rx_cal_cfg(uint64_t nae_base, int total_num_ports,
104 nlm_write_nae_reg(nae_base,
116 nlm_setup_tx_cal_cfg(uint64_t nae_base, int total_num_ports,
132 nlm_write_nae_reg(nae_base, NAE_EGR_NIOR_CAL_LEN_REG, tx_slots - 1);
140 nlm_write_nae_reg(nae_base,
152 nlm_deflate_frin_fifo_carving(uint64_t nae_base, int total_num_ports)
161 nlm_write_nae_reg(nae_base, NAE_FREE_IN_FIFO_CFG, value);
169 uint64_t nae_base;
176 nae_base = nlm_get_nae_regbase(node);
203 rx_config = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
208 nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
217 nlm_write_nae_reg(nae_base, NAE_POE_CLASS_SETUP_CFG, val);
222 nlm_setup_vfbid_mapping(uint64_t nae_base)
233 nlm_write_nae_reg(nae_base, NAE_VFBID_DESTMAP_CMD, val);
238 nlm_setup_flow_crc_poly(uint64_t nae_base, uint32_t poly)
240 nlm_write_nae_reg(nae_base, NAE_FLOW_CRC16_POLY_CFG, poly);
244 nlm_setup_iface_fifo_cfg(uint64_t nae_base, int maxports,
258 nlm_write_nae_reg(nae_base, NAE_IFACE_FIFO_CFG, reg);
264 nlm_setup_rx_base_config(uint64_t nae_base, int maxports,
281 nlm_write_nae_reg(nae_base, NAE_REG(7, 0, id), val);
286 nlm_setup_rx_buf_config(uint64_t nae_base, int maxports,
299 nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH_ADDR,
307 nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH, val);
308 nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH,
317 nlm_setup_freein_fifo_cfg(uint64_t nae_base, struct nae_port_config *cfg)
336 nlm_write_nae_reg(nae_base, NAE_FREE_IN_FIFO_CFG, reg);
358 nlm_program_flow_cfg(uint64_t nae_base, int port,
365 nlm_write_nae_reg(nae_base, NAE_FLOW_BASEMASK_CFG, val);
369 xlp_ax_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl,
383 nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val);
390 val = nlm_read_nae_reg(nae_base,
396 nlm_write_nae_reg(nae_base,
402 nlm_write_nae_reg(nae_base,
409 saved_data = nlm_read_nae_reg(nae_base,
412 nlm_write_nae_reg(nae_base,
421 while (((val = nlm_read_nae_reg(nae_base,
428 nlm_write_nae_reg(nae_base,
439 nlm_write_nae_reg(nae_base,
449 while (!((val = nlm_read_nae_reg(nae_base,
454 val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl));
456 nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl),
461 xlp_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl,
470 val = nlm_read_nae_reg(nae_base,
479 nlm_write_nae_reg(nae_base,
482 val = nlm_read_nae_reg(nae_base,
485 nlm_write_nae_reg(nae_base,
489 val = nlm_read_nae_reg(nae_base,
492 nlm_write_nae_reg(nae_base,
497 xlp_nae_config_lane_gmac(uint64_t nae_base, int cplx_mask)
519 nlm_write_nae_reg(nae_base,
531 nlm_write_nae_reg(nae_base,
538 nlm_write_nae_reg(nae_base,
544 xlp_nae_lane_reset_txpll(nae_base,
547 xlp_ax_nae_lane_reset_txpll(nae_base, 4,
559 xlp_nae_lane_reset_txpll(nae_base,
562 xlp_ax_nae_lane_reset_txpll(nae_base, block,
569 config_egress_fifo_carvings(uint64_t nae_base, int hwport, int start_ctxt,
592 nlm_write_nae_reg(nae_base, NAE_STG2_PMEM_PROG, data);
611 nlm_write_nae_reg(nae_base, NAE_EH_PMEM_PROG, data);
630 nlm_write_nae_reg(nae_base, NAE_FREE_PMEM_PROG, data);
649 nlm_write_nae_reg(nae_base, NAE_STR_PMEM_CMD, data);
664 nlm_write_nae_reg(nae_base, NAE_TX_PKT_PMEM_CMD1, offset);
669 nlm_write_nae_reg(nae_base, NAE_TX_PKT_PMEM_CMD0, data);
686 nlm_write_nae_reg(nae_base, NAE_TX_PKTLEN_PMEM_CMD, data);
693 config_egress_fifo_credits(uint64_t nae_base, int hwport, int start_ctxt,
709 nlm_write_nae_reg(nae_base, NAE_STG1_STG2CRDT_CMD, data);
721 nlm_write_nae_reg(nae_base, NAE_STG2_EHCRDT_CMD, data);
733 nlm_write_nae_reg(nae_base, NAE_EH_FREECRDT_CMD, data);
745 nlm_write_nae_reg(nae_base, NAE_STG2_STRCRDT_CMD, data);
750 nlm_config_freein_fifo_uniq_cfg(uint64_t nae_base, int port,
758 nlm_write_nae_reg(nae_base, NAE_FREEIN_FIFO_UNIQ_SZ_CFG, val);
763 nlm_config_ucore_iface_mask_cfg(uint64_t nae_base, int port,
770 nlm_write_nae_reg(nae_base, NAE_UCORE_IFACEMASK_CFG, val);
774 nlm_nae_init_netior(uint64_t nae_base, int nblocks)
798 nlm_write_nae_reg(nae_base, NAE_LANE_CFG_SOFTRESET, 0);
799 nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL3, ctrl3);
800 nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL2, ctrl2);
801 nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL1, ctrl1);
802 nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL1, 0x0);
807 nlm_nae_init_ingress(uint64_t nae_base, uint32_t desc_size)
812 rx_cfg = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
821 nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, rx_cfg);
822 nlm_write_nae_reg(nae_base, NAE_PARSER_CONFIG,
827 /*nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_THRESH, 33);*/
831 nlm_nae_init_egress(uint64_t nae_base)
835 tx_cfg = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG);
837 nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
844 nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
859 nlm_nae_init_ucore(uint64_t nae_base, int if_num, u_int ucore_mask)
864 nlm_write_nae_reg(nae_base, NAE_UCORE_IFACEMASK_CFG, ucfg);
877 nlm_setup_l2type(uint64_t nae_base, int hwport, uint32_t l2extlen,
889 nlm_write_nae_reg(nae_base, (NAE_L2_TYPE_PORT0 + hwport), val);
893 nlm_setup_l3ctable_mask(uint64_t nae_base, int hwport, uint32_t ptmask,
901 nlm_write_nae_reg(nae_base, NAE_L3_CTABLE_MASK0, val);
905 nlm_setup_l3ctable_even(uint64_t nae_base, int entry, uint32_t l3hdroff,
916 nlm_write_nae_reg(nae_base, (NAE_L3CTABLE0 + (entry * 2)), val);
920 nlm_setup_l3ctable_odd(uint64_t nae_base, int entry, uint32_t l3off0,
932 nlm_write_nae_reg(nae_base, (NAE_L3CTABLE0 + ((entry * 2) + 1)), val);
936 nlm_setup_l4ctable_even(uint64_t nae_base, int entry, uint32_t im,
948 nlm_write_nae_reg(nae_base, (NAE_L4CTABLE0 + (entry * 2)), val);
952 nlm_setup_l4ctable_odd(uint64_t nae_base, int entry, uint32_t l4off0,
961 nlm_write_nae_reg(nae_base, (NAE_L4CTABLE0 + ((entry * 2) + 1)), val);
965 nlm_enable_hardware_parser(uint64_t nae_base)
969 val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
971 nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val);
981 nlm_setup_l3ctable_even(nae_base, 0, 4, 1, 9, 1, 0x8847);
986 nlm_setup_l3ctable_odd(nae_base, 0, 9, 1, 12, 4, 16, 4);
991 nlm_setup_l3ctable_even(nae_base, 1, 0, 1, 9, 1, 0x0800);
996 nlm_setup_l3ctable_odd(nae_base, 1, 9, 1, 12, 4, 16, 4);
1001 nlm_setup_l3ctable_even(nae_base, 2, 0, 1, 6, 1, 0x86dd);
1006 nlm_setup_l3ctable_odd(nae_base, 2, 6, 1, 8, 16, 24, 16);
1011 nlm_setup_l3ctable_even(nae_base, 3, 0, 0, 9, 1, 0x0806);
1013 nlm_setup_l3ctable_odd(nae_base, 3, 0, 30, 0, 0, 0, 0);
1018 nlm_setup_l3ctable_even(nae_base, 4, 0, 0, 9, 1, 0x8906);
1027 nlm_setup_l3ctable_odd(nae_base, 4, 0, 28, 0, 0, 0, 0);
1032 nlm_setup_l3ctable_even(nae_base, 5, 0, 0, 9, 1, 0x8100);
1034 nlm_setup_l3ctable_odd(nae_base, 5, 0, 31, 0, 0, 0, 0);
1040 nlm_setup_l3ctable_even(nae_base, 6, 0, 0, 9, 1, 0x88a8);
1042 nlm_setup_l3ctable_odd(nae_base, 6, 0, 31, 0, 0, 0, 0);
1047 nlm_setup_l3ctable_even(nae_base, 7, 0, 0, 9, 1, 0x9100);
1049 nlm_setup_l3ctable_odd(nae_base, 7, 0, 31, 0, 0, 0, 0);
1054 nlm_setup_l3ctable_even(nae_base, 8, 0, 0, 9, 1, 0x8870);
1056 nlm_setup_l3ctable_odd(nae_base, 8, 0, 31, 0, 0, 0, 0);
1061 nlm_setup_l3ctable_even(nae_base, 9, 0, 0, 9, 1, 0x8848);
1063 nlm_setup_l3ctable_odd(nae_base, 9, 0, 31, 0, 0, 0, 0);
1068 nlm_setup_l3ctable_even(nae_base, 10, 0, 0, 9, 1, 0x88e5);
1070 nlm_setup_l3ctable_odd(nae_base, 10, 0, 31, 0, 0, 0, 0);
1075 nlm_setup_l3ctable_even(nae_base, 11, 0, 0, 9, 1, 0x88f7);
1083 nlm_setup_l3ctable_odd(nae_base, 11, 0, 31, 31, 2, 0, 0);
1089 nlm_setup_l3ctable_even(nae_base, 12, 0, 0, 9, 1, 0xc021);
1095 nlm_setup_l3ctable_odd(nae_base, 12, 0, 4, 0, 0, 0, 0);
1101 nlm_setup_l3ctable_even(nae_base, 13, 0, 0, 9, 1, 0xc025);
1103 nlm_setup_l3ctable_odd(nae_base, 13, 0, 31, 0, 0, 0, 0);
1108 nlm_setup_l3ctable_even(nae_base, 14, 0, 0, 9, 1, 0x8864);
1110 nlm_setup_l3ctable_odd(nae_base, 14, 0, 31, 0, 0, 0, 0);
1115 nlm_setup_l3ctable_even(nae_base, 15, 0, 0, 0, 0, 0x0000);
1117 nlm_setup_l3ctable_odd(nae_base, 15, 0, 31, 0, 0, 0, 0);
1126 nlm_setup_l4ctable_even(nae_base, 0, 0, 0, 1, 0, 0, 0x6);
1129 nlm_setup_l4ctable_odd(nae_base, 0, 0, 15, 15, 5);
1134 nlm_setup_l4ctable_even(nae_base, 1, 0, 0, 1, 0, 0, 0x11);
1137 nlm_setup_l4ctable_odd(nae_base, 1, 0, 8, 0, 0);
1142 nlm_setup_l4ctable_even(nae_base, 2, 0, 0, 1, 0, 0, 0x84);
1146 nlm_setup_l4ctable_odd(nae_base, 2, 0, 12, 0, 0);
1151 nlm_setup_l4ctable_even(nae_base, 3, 0, 0, 1, 0, 0, 0x1b);
1155 nlm_setup_l4ctable_odd(nae_base, 3, 0, 15, 15, 3);
1160 nlm_setup_l4ctable_even(nae_base, 4, 0, 0, 1, 0, 0, 0x21);
1164 nlm_setup_l4ctable_odd(nae_base, 4, 0, 15, 15, 1);
1169 nlm_setup_l4ctable_even(nae_base, 5, 0, 0, 1, 0, 0, 0x29);
1172 nlm_setup_l4ctable_odd(nae_base, 5, 0, 15, 15, 5);
1177 nlm_setup_l4ctable_even(nae_base, 6, 0, 0, 1, 0, 0, 0x04);
1180 nlm_setup_l4ctable_odd(nae_base, 6, 0, 15, 15, 5);
1185 nlm_setup_l4ctable_even(nae_base, 7, 0, 0, 1, 0, 0, 0x0);
1187 nlm_setup_l4ctable_odd(nae_base, 7, 0, 15, 15, 5);
1191 nlm_enable_hardware_parser_per_port(uint64_t nae_base, int block, int port)
1197 nlm_setup_l2type(nae_base, hwport, 0, 0, 0, 0, 0, 1);
1200 nlm_setup_l3ctable_mask(nae_base, hwport, 1, 0);
1204 nlm_prepad_enable(uint64_t nae_base, int size)
1208 val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
1211 nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val);
1215 nlm_setup_1588_timer(uint64_t nae_base, struct nae_port_config *cfg)
1221 nlm_write_nae_reg(nae_base, NAE_1588_PTP_USER_VALUE_HI, hi);
1222 nlm_write_nae_reg(nae_base, NAE_1588_PTP_USER_VALUE_LO, lo);
1226 nlm_write_nae_reg(nae_base, NAE_1588_PTP_OFFSET_HI, hi);
1227 nlm_write_nae_reg(nae_base, NAE_1588_PTP_OFFSET_LO, lo);
1231 nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR1_HI, hi);
1232 nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR1_LO, lo);
1236 nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR2_HI, hi);
1237 nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR2_LO, lo);
1241 nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR3_HI, hi);
1242 nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR3_LO, lo);
1244 nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_INTG,
1246 nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_NUM,
1248 nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_DEN,
1251 val = nlm_read_nae_reg(nae_base, NAE_1588_PTP_CONTROL);
1253 nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val | (0x1 << 1));
1254 nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val);
1256 nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val | (0x1 << 6));
1257 nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val);
1261 nlm_mac_enable(uint64_t nae_base, int nblock, int port_type, int port)
1269 netwk_inf = nlm_read_nae_reg(nae_base,
1271 nlm_write_nae_reg(nae_base,
1275 mac_cfg1 = nlm_read_nae_reg(nae_base,
1277 nlm_write_nae_reg(nae_base,
1284 xaui_cfg = nlm_read_nae_reg(nae_base,
1286 nlm_write_nae_reg(nae_base,
1298 nlm_mac_disable(uint64_t nae_base, int nblock, int port_type, int port)
1306 mac_cfg1 = nlm_read_nae_reg(nae_base,
1308 nlm_write_nae_reg(nae_base,
1313 netwk_inf = nlm_read_nae_reg(nae_base,
1315 nlm_write_nae_reg(nae_base,
1321 xaui_cfg = nlm_read_nae_reg(nae_base,
1323 nlm_write_nae_reg(nae_base,
1338 nlm_nae_set_ior_credit(uint64_t nae_base, uint32_t ifmask, uint32_t valmask)
1342 tx_ior_credit = nlm_read_nae_reg(nae_base, NAE_TX_IORCRDT_INIT);
1345 nlm_write_nae_reg(nae_base, NAE_TX_IORCRDT_INIT, tx_ior_credit);
1347 tx_config = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG);
1349 nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
1351 nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
1356 nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type,
1365 netwk_inf = nlm_read_nae_reg(nae_base,
1368 nlm_write_nae_reg(nae_base,
1371 nlm_nae_set_ior_credit(nae_base, 0xf << port, 0xf << port);
1375 nlm_nae_set_ior_credit(nae_base, 0xff << port, 0xff << port);
1379 nlm_nae_set_ior_credit(nae_base, 0x1 << port, 0);
1391 netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
1394 nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf);
1398 nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf);
1401 mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
1402 nlm_write_nae_reg(nae_base, conf1_reg,
1409 nlm_write_nae_reg(nae_base,
1417 mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
1418 nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1U << 31));
1422 netior_ctrl3 = nlm_read_nae_reg(nae_base, iface_ctrl3_reg);
1423 nlm_write_nae_reg(nae_base, iface_ctrl3_reg,
1427 mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
1428 nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(0x5));
1429 netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
1430 nlm_write_nae_reg(nae_base, iface_ctrl_reg,
1434 netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
1435 nlm_write_nae_reg(nae_base, iface_ctrl_reg,
1439 netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
1440 nlm_write_nae_reg(nae_base, iface_ctrl_reg,
1444 mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
1445 nlm_write_nae_reg(nae_base, conf1_reg,
1450 nlm_nae_init_ingress(nae_base, desc_size);
1451 nlm_nae_init_egress(nae_base);