dev/net/mdio.c

45 nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block,
61 	mdio_ld_cmd = nlm_read_nae_reg(nae_base,
64 		nlm_write_nae_reg(nae_base,
69 	nlm_write_nae_reg(nae_base,
74 	nlm_write_nae_reg(nae_base,
79 	while(nlm_read_nae_reg(nae_base,
84 	nlm_write_nae_reg(nae_base,
89 	return nlm_read_nae_reg(nae_base,
95 nlm_int_gmac_mdio_write(uint64_t nae_base, int bus, int block,
111 	mdio_ld_cmd = nlm_read_nae_reg(nae_base,
114 		nlm_write_nae_reg(nae_base,
120 	nlm_write_nae_reg(nae_base,
124 	nlm_write_nae_reg(nae_base,
128 	nlm_write_nae_reg(nae_base,
133 	while(nlm_read_nae_reg(nae_base,
138 	nlm_write_nae_reg(nae_base,
146 nlm_int_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
155 	nlm_write_nae_reg(nae_base,
159 	nlm_write_nae_reg(nae_base,
178 nlm_gmac_mdio_read(uint64_t nae_base, int bus, int block,
184 	mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
187 		nlm_write_nae_reg(nae_base,
190 		while(nlm_read_nae_reg(nae_base,
204 	nlm_write_nae_reg(nae_base,
208 	nlm_write_nae_reg(nae_base,
213 	while(nlm_read_nae_reg(nae_base,
217 	nlm_write_nae_reg(nae_base,
222 	return nlm_read_nae_reg(nae_base,
239 nlm_gmac_mdio_write(uint64_t nae_base, int bus, int block,
245 	mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
248 		nlm_write_nae_reg(nae_base,
251 		while(nlm_read_nae_reg(nae_base,
258 	nlm_write_nae_reg(nae_base,
270 	nlm_write_nae_reg(nae_base,
274 	nlm_write_nae_reg(nae_base,
280 	while(nlm_read_nae_reg(nae_base,
284 	nlm_write_nae_reg(nae_base,
301 nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
306 	ctrlval = nlm_read_nae_reg(nae_base,
314 	nlm_write_nae_reg(nae_base,
317 	nlm_write_nae_reg(nae_base,
326 nlm_mdio_reset_all(uint64_t nae_base)
329 	nlm_int_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
331 	nlm_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
332 	nlm_gmac_mdio_reset(nae_base, 1, BLOCK_7, LANE_CFG);