mips/atheros/if_arge.c

417 	ARGE_WRITE(sc, AR71XX_MAC_CFG1,
423 	ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
425 	ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
600 	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | mdio_div);
602 	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, mdio_div);
907 	ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
910 	ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
913 	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
932 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
933 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
937 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
938 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
941 	ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
944 	ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
1319 	ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
1320 	ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
1321 	ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
1323 	ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
1364 	ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
1365 	ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
1367 	ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
1368 	ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
1372 		ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1378 		ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1383 	ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
1385 	ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
1448 	ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
1449 	ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
1452 	ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1455 	ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1613 	ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
1706 	ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1772 				ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1780 				ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
2388 		ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
2444 		ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
2512 		ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2556 		ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2562 		ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
2578 		ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
2579 		ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
2590 		ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
2595 			ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
2629 	ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);