Lines Matching refs:mBIT
46 #define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_INT mBIT(3)
47 #define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT mBIT(7)
49 mBIT(11)
52 #define VXGE_HAL_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT mBIT(3)
56 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT mBIT(0)
57 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT mBIT(1)
58 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT mBIT(2)
59 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT mBIT(3)
60 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT mBIT(4)
61 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT mBIT(5)
62 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT mBIT(6)
63 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT mBIT(7)
64 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT mBIT(8)
65 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT mBIT(9)
66 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT mBIT(10)
67 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT mBIT(11)
68 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT mBIT(12)
69 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT mBIT(13)
70 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT mBIT(14)
71 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT mBIT(15)
72 #define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT mBIT(16)
87 #define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG mBIT(0)
99 #define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT mBIT(0)
100 #define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PCI_INT mBIT(3)
101 #define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT mBIT(7)
105 #define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PIC_INT mBIT(0)
106 #define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT mBIT(3)
107 #define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_XMAC_INT mBIT(7)
112 mBIT(3)
113 #define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM mBIT(7)
114 #define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_VPATH_TO_SRPCIM_ALARM_INT mBIT(11)
117 #define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR mBIT(3)
118 #define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR mBIT(7)
119 #define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR mBIT(11)
120 #define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT mBIT(15)
121 #define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET mBIT(19)
122 #define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS mBIT(23)
126 #define VXGE_HAL_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM mBIT(3)
139 #define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN mBIT(19)
140 #define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN mBIT(23)
141 #define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN mBIT(27)
142 #define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN mBIT(31)
143 #define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN mBIT(35)
144 #define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN mBIT(39)
151 #define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_ONE_SHOT mBIT(11)
152 #define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_TIMER_EN mBIT(15)
157 #define VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK mBIT(0)
159 #define VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK mBIT(0)
161 #define VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT mBIT(0)
163 #define VXGE_HAL_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG mBIT(7)
165 #define VXGE_HAL_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED mBIT(7)
169 #define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK mBIT(3)
170 #define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR mBIT(7)
178 #define VXGE_HAL_ONE_CFG_SR_COPY_ONE_CFG_RDY mBIT(7)
182 #define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_ENABLE_IWARP mBIT(7)
187 #define VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT mBIT(3)
190 #define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT mBIT(3)
191 #define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK mBIT(7)
193 mBIT(11)
194 #define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED mBIT(15)
208 #define VXGE_HAL_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY mBIT(0)
210 #define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_START mBIT(0)
211 #define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_END mBIT(1)
212 #define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_START mBIT(2)
213 #define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_END mBIT(3)
214 #define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_START mBIT(4)
215 #define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_END mBIT(5)
216 #define VXGE_HAL_WDE_CFG_NS0_MWB_OPT_EN mBIT(6)
217 #define VXGE_HAL_WDE_CFG_NS0_QB_OPT_EN mBIT(7)
218 #define VXGE_HAL_WDE_CFG_NS0_MPSB_OPT_EN mBIT(8)
219 #define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_START mBIT(9)
220 #define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_END mBIT(10)
221 #define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_START mBIT(11)
222 #define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_END mBIT(12)
223 #define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_START mBIT(13)
224 #define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_END mBIT(14)
225 #define VXGE_HAL_WDE_CFG_NS1_MWB_OPT_EN mBIT(15)
226 #define VXGE_HAL_WDE_CFG_NS1_QB_OPT_EN mBIT(16)
227 #define VXGE_HAL_WDE_CFG_NS1_MPSB_OPT_EN mBIT(17)
228 #define VXGE_HAL_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR mBIT(19)