Lines Matching refs:mBIT
41 #define VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT mBIT(0)
44 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR mBIT(4)
45 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_DECC mBIT(5)
46 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC mBIT(6)
47 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC mBIT(7)
48 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_SECC mBIT(29)
49 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC mBIT(30)
50 #define VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC mBIT(31)
63 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_OFF mBIT(15)
64 #define VXGE_HAL_G3FBCT_CONFIG1_IGNORE_BEM mBIT(23)
66 #define VXGE_HAL_G3FBCT_CONFIG1_CMD_START_PHASE mBIT(39)
74 #define VXGE_HAL_G3FBCT_CONFIG2_DEFINE_CAD mBIT(31)
75 #define VXGE_HAL_G3FBCT_CONFIG2_DEFINE_NOP_AD mBIT(39)
80 #define VXGE_HAL_G3FBCT_INIT0_MRS_DLL mBIT(23)
81 #define VXGE_HAL_G3FBCT_INIT0_MRS_TM mBIT(39)
83 #define VXGE_HAL_G3FBCT_INIT0_MRS_BT mBIT(55)
87 #define VXGE_HAL_G3FBCT_INIT1_EMRS_AD_TER mBIT(15)
88 #define VXGE_HAL_G3FBCT_INIT1_EMRS_ID mBIT(23)
89 #define VXGE_HAL_G3FBCT_INIT1_EMRS_RON mBIT(39)
90 #define VXGE_HAL_G3FBCT_INIT1_EMRS_AL mBIT(47)
95 #define VXGE_HAL_G3FBCT_INIT2_START_INI mBIT(15)
110 #define VXGE_HAL_G3FBCT_INIT4_CKE_INIT_VAL mBIT(31)
113 #define VXGE_HAL_G3FBCT_INIT4_ICTRL_INIT_DONE mBIT(55)
114 #define VXGE_HAL_G3FBCT_INIT4_IOCAL_WAIT_DISABLE mBIT(63)
168 #define VXGE_HAL_G3FBCT_TEST01_TEST_MODE mBIT(23)
169 #define VXGE_HAL_G3FBCT_TEST01_TEST_GO mBIT(31)
170 #define VXGE_HAL_G3FBCT_TEST01_TEST_DONE mBIT(39)
172 #define VXGE_HAL_G3FBCT_TEST01_TEST_DATA_ADDR mBIT(63)
211 #define VXGE_HAL_G3FBCT_LOOP_BACK_MODE mBIT(39)
212 #define VXGE_HAL_G3FBCT_LOOP_BACK_GO mBIT(47)
213 #define VXGE_HAL_G3FBCT_LOOP_BACK_DONE mBIT(55)
253 #define VXGE_HAL_G3FBCT_TRAN_AP_CNT_UPDATE mBIT(39)
255 #define VXGE_HAL_G3FBCT_G3BIST_DISABLE_MAIN mBIT(7)
256 #define VXGE_HAL_G3FBCT_G3BIST_DISABLE_ICTRL mBIT(15)
262 #define VXGE_HAL_WRDMA_INT_STATUS_RC_ALARM_RC_INT mBIT(0)
263 #define VXGE_HAL_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT mBIT(1)
264 #define VXGE_HAL_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT mBIT(2)
265 #define VXGE_HAL_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT mBIT(3)
266 #define VXGE_HAL_WRDMA_INT_STATUS_RDA_ERR_RDA_INT mBIT(6)
267 #define VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT mBIT(8)
268 #define VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT mBIT(9)
269 #define VXGE_HAL_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT mBIT(12)
270 #define VXGE_HAL_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT mBIT(13)
271 #define VXGE_HAL_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT mBIT(14)
272 #define VXGE_HAL_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT mBIT(15)
273 #define VXGE_HAL_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT mBIT(16)
274 #define VXGE_HAL_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT mBIT(17)
277 #define VXGE_HAL_RC_ALARM_REG_FTC_SM_ERR mBIT(0)
278 #define VXGE_HAL_RC_ALARM_REG_FTC_SM_PHASE_ERR mBIT(1)
279 #define VXGE_HAL_RC_ALARM_REG_BTDWM_SM_ERR mBIT(2)
280 #define VXGE_HAL_RC_ALARM_REG_BTC_SM_ERR mBIT(3)
281 #define VXGE_HAL_RC_ALARM_REG_BTDCM_SM_ERR mBIT(4)
282 #define VXGE_HAL_RC_ALARM_REG_BTDRM_SM_ERR mBIT(5)
283 #define VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR mBIT(6)
284 #define VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR mBIT(7)
285 #define VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR mBIT(8)
286 #define VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR mBIT(9)
287 #define VXGE_HAL_RC_ALARM_REG_RMM_SM_ERR mBIT(10)
288 #define VXGE_HAL_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR mBIT(12)
292 #define VXGE_HAL_RXDRM_SM_ERR_REG_PRC_VP(n) mBIT(n)
296 #define VXGE_HAL_RXDCM_SM_ERR_REG_PRC_VP(n) mBIT(n)
300 #define VXGE_HAL_RXDWM_SM_ERR_REG_PRC_VP(n) mBIT(n)
304 #define VXGE_HAL_RDA_ERR_REG_RDA_SM0_ERR_ALARM mBIT(0)
305 #define VXGE_HAL_RDA_ERR_REG_RDA_MISC_ERR mBIT(1)
306 #define VXGE_HAL_RDA_ERR_REG_RDA_PCIX_ERR mBIT(2)
307 #define VXGE_HAL_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR mBIT(3)
308 #define VXGE_HAL_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR mBIT(4)
309 #define VXGE_HAL_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR mBIT(5)
310 #define VXGE_HAL_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR mBIT(6)
311 #define VXGE_HAL_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR mBIT(7)
315 #define VXGE_HAL_RDA_ECC_DB_REG_RDA_RXD_ERR(n) mBIT(n)
319 #define VXGE_HAL_RDA_ECC_SG_REG_RDA_RXD_ERR(n) mBIT(n)
323 #define VXGE_HAL_RQA_ERR_REG_RQA_SM_ERR_ALARM mBIT(0)
327 #define VXGE_HAL_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n) mBIT(n)
331 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB mBIT(0)
332 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG mBIT(1)
333 #define VXGE_HAL_ROCRC_ALARM_REG_NOA_NMA_SM_ERR mBIT(2)
334 #define VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB mBIT(3)
335 #define VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG mBIT(4)
336 #define VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB mBIT(5)
337 #define VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG mBIT(6)
338 #define VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB mBIT(11)
339 #define VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG mBIT(12)
340 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR mBIT(13)
341 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR mBIT(14)
342 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR mBIT(15)
343 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR mBIT(16)
344 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR mBIT(17)
345 #define VXGE_HAL_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR mBIT(18)
346 #define VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW mBIT(19)
347 #define VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW mBIT(20)
348 #define VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW mBIT(21)
349 #define VXGE_HAL_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR mBIT(22)
353 #define VXGE_HAL_WDE0_ALARM_REG_WDE0_DCC_SM_ERR mBIT(0)
354 #define VXGE_HAL_WDE0_ALARM_REG_WDE0_PRM_SM_ERR mBIT(1)
355 #define VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_SM_ERR mBIT(2)
356 #define VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_CMD_ERR mBIT(3)
357 #define VXGE_HAL_WDE0_ALARM_REG_WDE0_PCR_SM_ERR mBIT(4)
361 #define VXGE_HAL_WDE1_ALARM_REG_WDE1_DCC_SM_ERR mBIT(0)
362 #define VXGE_HAL_WDE1_ALARM_REG_WDE1_PRM_SM_ERR mBIT(1)
363 #define VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_SM_ERR mBIT(2)
364 #define VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_CMD_ERR mBIT(3)
365 #define VXGE_HAL_WDE1_ALARM_REG_WDE1_PCR_SM_ERR mBIT(4)
369 #define VXGE_HAL_WDE2_ALARM_REG_WDE2_DCC_SM_ERR mBIT(0)
370 #define VXGE_HAL_WDE2_ALARM_REG_WDE2_PRM_SM_ERR mBIT(1)
371 #define VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_SM_ERR mBIT(2)
372 #define VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_CMD_ERR mBIT(3)
373 #define VXGE_HAL_WDE2_ALARM_REG_WDE2_PCR_SM_ERR mBIT(4)
377 #define VXGE_HAL_WDE3_ALARM_REG_WDE3_DCC_SM_ERR mBIT(0)
378 #define VXGE_HAL_WDE3_ALARM_REG_WDE3_PRM_SM_ERR mBIT(1)
379 #define VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_SM_ERR mBIT(2)
380 #define VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_CMD_ERR mBIT(3)
381 #define VXGE_HAL_WDE3_ALARM_REG_WDE3_PCR_SM_ERR mBIT(4)
386 #define VXGE_HAL_RC_CFG_RXD_RD_RO mBIT(12)
387 #define VXGE_HAL_RC_CFG_FIXED_BUFFER_SIZE mBIT(13)
388 #define VXGE_HAL_RC_CFG_ENABLE_VP_CFG_CHANGE_WHILE_BUSY mBIT(14)
389 #define VXGE_HAL_RC_CFG_PRESERVE_BUFFER_SIZE mBIT(15)
391 #define VXGE_HAL_ECC_CFG_RXD_RC_ECC_ENABLE_N mBIT(0)
392 #define VXGE_HAL_ECC_CFG_RXD_RHS_ECC_ENABLE_N mBIT(1)
393 #define VXGE_HAL_ECC_CFG_NOA_IMMM_ECC_ENABLE_N mBIT(4)
394 #define VXGE_HAL_ECC_CFG_UDQ_UMQM_ECC_ENABLE_N mBIT(5)
395 #define VXGE_HAL_ECC_CFG_RCBM_CQB_ECC_ENABLE_N mBIT(7)
735 #define VXGE_HAL_RX_QUEUE_SELECT_NUMBER(n) mBIT(n)
736 #define VXGE_HAL_RX_QUEUE_SELECT_ENABLE_CODE mBIT(15)
737 #define VXGE_HAL_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY mBIT(23)
739 #define VXGE_HAL_RQA_VPBP_CTRL_WR_XON_DIS mBIT(15)
740 #define VXGE_HAL_RQA_VPBP_CTRL_ROCRC_DIS mBIT(23)
741 #define VXGE_HAL_RQA_VPBP_CTRL_TXPE_DIS mBIT(31)
743 #define VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_DIS mBIT(0)
744 #define VXGE_HAL_RX_MULTI_CAST_CTRL_FRM_DROP_DIS mBIT(1)
750 #define VXGE_HAL_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW mBIT(32)
751 #define VXGE_HAL_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY mBIT(33)
756 #define VXGE_HAL_NOA_CTRL_IGNORE_KDFC_IF_STATUS mBIT(16)
762 #define VXGE_HAL_PHASE_CFG_QCC_WR_PHASE_EN mBIT(0)
763 #define VXGE_HAL_PHASE_CFG_QCC_RD_PHASE_EN mBIT(3)
764 #define VXGE_HAL_PHASE_CFG_IMMM_WR_PHASE_EN mBIT(7)
765 #define VXGE_HAL_PHASE_CFG_IMMM_RD_PHASE_EN mBIT(11)
766 #define VXGE_HAL_PHASE_CFG_UMQM_WR_PHASE_EN mBIT(15)
767 #define VXGE_HAL_PHASE_CFG_UMQM_RD_PHASE_EN mBIT(19)
768 #define VXGE_HAL_PHASE_CFG_RCBM_WR_PHASE_EN mBIT(23)
769 #define VXGE_HAL_PHASE_CFG_RCBM_RD_PHASE_EN mBIT(27)
770 #define VXGE_HAL_PHASE_CFG_RXD_RC_WR_PHASE_EN mBIT(31)
771 #define VXGE_HAL_PHASE_CFG_RXD_RC_RD_PHASE_EN mBIT(35)
772 #define VXGE_HAL_PHASE_CFG_RXD_RHS_WR_PHASE_EN mBIT(39)
773 #define VXGE_HAL_PHASE_CFG_RXD_RHS_RD_PHASE_EN mBIT(43)
781 #define VXGE_HAL_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT mBIT(7)
782 #define VXGE_HAL_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT mBIT(15)
785 #define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR mBIT(7)
786 #define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR mBIT(15)
787 #define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM mBIT(23)
788 #define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1 mBIT(32)
789 #define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR mBIT(39)
792 #define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR mBIT(7)
793 #define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR mBIT(15)
794 #define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM mBIT(23)
795 #define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1 mBIT(32)
796 #define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR mBIT(39)
798 #define VXGE_HAL_USDC_ERR_REG_USDC_FIFO_ECC_SG_ERR mBIT(4)
799 #define VXGE_HAL_USDC_ERR_REG_USDC_WA_ECC_SG_ERR mBIT(5)
800 #define VXGE_HAL_USDC_ERR_REG_USDC_CA_ECC_SG_ERR mBIT(6)
801 #define VXGE_HAL_USDC_ERR_REG_USDC_SA_ECC_SG_ERR mBIT(7)
802 #define VXGE_HAL_USDC_ERR_REG_USDC_FIFO_ECC_DB_ERR mBIT(12)
803 #define VXGE_HAL_USDC_ERR_REG_USDC_WA_ECC_DB_ERR mBIT(13)
804 #define VXGE_HAL_USDC_ERR_REG_USDC_CA_ECC_DB_ERR mBIT(14)
805 #define VXGE_HAL_USDC_ERR_REG_USDC_SA_ECC_DB_ERR mBIT(15)
806 #define VXGE_HAL_USDC_ERR_REG_USDC_USDC_SM_ERR_ALARM mBIT(23)
807 #define VXGE_HAL_USDC_ERR_REG_USDC_USDC_MISC_ERR_0 mBIT(30)
808 #define VXGE_HAL_USDC_ERR_REG_USDC_USDC_MISC_ERR_1 mBIT(31)
809 #define VXGE_HAL_USDC_ERR_REG_USDC_USDC_PCI_ERR mBIT(39)
812 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_FIFO_ECC_SG_ERR mBIT(4)
813 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_WA_ECC_SG_ERR mBIT(5)
814 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_CA_ECC_SG_ERR mBIT(6)
815 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_SA_ECC_SG_ERR mBIT(7)
816 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_FIFO_ECC_DB_ERR mBIT(12)
817 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_WA_ECC_DB_ERR mBIT(13)
818 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_CA_ECC_DB_ERR mBIT(14)
819 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_SA_ECC_DB_ERR mBIT(15)
820 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_SM_ERR_ALARM mBIT(23)
821 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_MISC_ERR_0 mBIT(30)
822 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_MISC_ERR_1 mBIT(31)
823 #define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_PCI_ERR mBIT(39)
825 #define VXGE_HAL_KDFC_VP_PARTITION_0_ENABLE mBIT(0)
1494 #define VXGE_HAL_KDFC_PDA_MONITOR_KDFC_ACCEPT mBIT(7)
1500 #define VXGE_HAL_KDFC_MP_MONITOR_KDFC_ACCEPT mBIT(7)
1506 #define VXGE_HAL_KDFC_PE_MONITOR_KDFC_CREDIT mBIT(7)
1513 #define VXGE_HAL_KDFC_READ_CNTRL_KDFC_FREEZE mBIT(7)
1515 #define VXGE_HAL_KDFC_READ_CNTRL_KDFC_WORD_SEL mBIT(23)
1520 #define VXGE_HAL_KDFC_FORCE_VALID_CTRL_FORCE_VALID mBIT(7)
1524 #define VXGE_HAL_KDFC_ECC_CTRL_ECC_DISABLE mBIT(7)
1526 #define VXGE_HAL_KDFC_VPBP_CTRL_RD_XON_DIS mBIT(7)
1527 #define VXGE_HAL_KDFC_VPBP_CTRL_ROCRC_DIS mBIT(23)
1528 #define VXGE_HAL_KDFC_VPBP_CTRL_H2L_DIS mBIT(31)
1529 #define VXGE_HAL_KDFC_VPBP_CTRL_MSG_ONE_DIS mBIT(39)
1530 #define VXGE_HAL_KDFC_VPBP_CTRL_MSG_DMQ_DIS mBIT(47)
1531 #define VXGE_HAL_KDFC_VPBP_CTRL_PDA_DIS mBIT(55)
1535 #define VXGE_HAL_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT mBIT(3)
1536 #define VXGE_HAL_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT mBIT(7)
1537 #define VXGE_HAL_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT mBIT(11)
1565 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR mBIT(32)
1566 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR mBIT(33)
1567 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR mBIT(34)
1568 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR mBIT(35)
1569 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR mBIT(36)
1570 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR mBIT(37)
1571 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR mBIT(38)
1572 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR mBIT(39)
1581 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR mBIT(60)
1582 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR mBIT(61)
1586 #define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR mBIT(0)
1587 #define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR mBIT(1)
1588 #define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR mBIT(2)
1589 #define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR mBIT(3)
1593 #define VXGE_HAL_RXMAC_GEN_CFG_SCALE_RMAC_UTIL mBIT(11)
1595 #define VXGE_HAL_RXMAC_AUTHORIZE_ALL_ADDR_VP(n) mBIT(n)
1597 #define VXGE_HAL_RXMAC_AUTHORIZE_ALL_VID_VP(n) mBIT(n)
1601 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_LOW_UP_CROSSED mBIT(3)
1602 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_LOW_DOWN_CROSSED mBIT(7)
1603 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_HIGH_UP_CROSSED mBIT(11)
1604 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_HIGH_DOWN_CROSSED mBIT(15)
1605 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED0_UP_CROSSED mBIT(35)
1606 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED0_DOWN_CROSSED mBIT(39)
1607 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED1_UP_CROSSED mBIT(43)
1608 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED1_DOWN_CROSSED mBIT(47)
1609 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED2_UP_CROSSED mBIT(51)
1610 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED2_DOWN_CROSSED mBIT(55)
1611 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED3_UP_CROSSED mBIT(59)
1612 #define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED3_DOWN_CROSSED mBIT(63)
1622 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN mBIT(35)
1626 #define VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN mBIT(3)
1627 #define VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS mBIT(7)
1628 #define VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM mBIT(11)
1629 #define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_FCS_ERR mBIT(15)
1630 #define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_LONG_ERR mBIT(19)
1631 #define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR mBIT(23)
1632 #define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH mBIT(27)
1637 #define VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN mBIT(3)
1639 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN mBIT(3)
1640 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN mBIT(7)
1642 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_DUAL_THR mBIT(15)
1644 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR mBIT(39)
1645 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR mBIT(43)
1646 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN mBIT(47)
1648 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL mBIT(59)
1652 #define VXGE_HAL_RXMAC_RED_CFG0_PORT_RED_EN_VP(n) mBIT(n)
1654 #define VXGE_HAL_RXMAC_RED_CFG1_PORT_FINE_EN mBIT(3)
1655 #define VXGE_HAL_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE mBIT(11)
1657 #define VXGE_HAL_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n) mBIT(n)
1663 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR mBIT(23)
1667 #define VXGE_HAL_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD mBIT(3)
1671 #define VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR mBIT(3)
1672 #define VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N mBIT(7)
1673 #define VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO mBIT(18)
1674 #define VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS mBIT(19)
1675 #define VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING mBIT(23)
1676 #define VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN mBIT(27)
1677 #define VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE mBIT(35)
1678 #define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR mBIT(39)
1679 #define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR mBIT(43)
1680 #define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR mBIT(47)
1681 #define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR mBIT(51)
1682 #define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR mBIT(55)
1683 #define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR mBIT(59)
1684 #define VXGE_HAL_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN mBIT(63)
1686 #define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH mBIT(3)
1687 #define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH mBIT(7)
1688 #define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH mBIT(11)
1689 #define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH mBIT(15)
1690 #define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF mBIT(19)
1691 #define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG mBIT(23)
1695 #define VXGE_HAL_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY mBIT(3)
1697 #define VXGE_HAL_RTS_MGR_CFG0_ICMP_TRASH mBIT(35)
1698 #define VXGE_HAL_RTS_MGR_CFG0_TCPSYN_TRASH mBIT(39)
1699 #define VXGE_HAL_RTS_MGR_CFG0_ZL4PYLD_TRASH mBIT(43)
1700 #define VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH mBIT(47)
1701 #define VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH mBIT(51)
1702 #define VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH mBIT(55)
1703 #define VXGE_HAL_RTS_MGR_CFG0_IPFRAG_TRASH mBIT(59)
1705 #define VXGE_HAL_RTS_MGR_CFG1_DA_ACTIVE_TABLE mBIT(3)
1706 #define VXGE_HAL_RTS_MGR_CFG1_PN_ACTIVE_TABLE mBIT(7)
1724 #define VXGE_HAL_RTS_MGR_STEER_CTRL_WE mBIT(7)
1726 #define VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE mBIT(15)
1727 #define VXGE_HAL_RTS_MGR_STEER_CTRL_BEHAV_TBL_SEL mBIT(23)
1728 #define VXGE_HAL_RTS_MGR_STEER_CTRL_TABLE_SEL mBIT(27)
1730 #define VXGE_HAL_RTS_MGR_STEER_CTRL_RMACJ_STATUS mBIT(0)
1741 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXC_CHAR1 mBIT(7)
1744 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXC_CHAR2 mBIT(23)
1746 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_BEHAV_CHAR2_NEAR_CHAR1 mBIT(39)
1750 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE0 mBIT(7)
1752 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE1 mBIT(23)
1754 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE2 mBIT(39)
1756 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE3 mBIT(55)
1759 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE0 mBIT(7)
1761 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE1 mBIT(23)
1763 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE2 mBIT(39)
1765 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE3 mBIT(55)
1768 #define VXGE_HAL_XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_NEAR_COL1 mBIT(7)
1771 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_CTRL_PORT_EN mBIT(3)
1772 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_CTRL_PORT_READBACK mBIT(7)
1791 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_LOW_UP_CROSSED mBIT(3)
1792 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_LOW_DOWN_CROSSED mBIT(7)
1793 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_HIGH_UP_CROSSED mBIT(11)
1794 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_HIGH_DOWN_CROSSED mBIT(15)
1795 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR0_UP_CROSSED mBIT(35)
1796 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR0_DOWN_CROSSED mBIT(39)
1797 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR1_UP_CROSSED mBIT(43)
1798 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR1_DOWN_CROSSED mBIT(47)
1799 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR2_UP_CROSSED mBIT(51)
1800 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR2_DOWN_CROSSED mBIT(55)
1801 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR3_UP_CROSSED mBIT(59)
1802 #define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR3_DOWN_CROSSED mBIT(63)
1806 #define VXGE_HAL_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT mBIT(3)
1808 mBIT(7)
1810 mBIT(11)
1811 #define VXGE_HAL_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT mBIT(15)
1812 #define VXGE_HAL_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT mBIT(19)
1813 #define VXGE_HAL_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT mBIT(23)
1816 #define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED mBIT(7)
1817 #define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED mBIT(11)
1818 #define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU mBIT(15)
1819 #define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED mBIT(19)
1820 #define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED mBIT(23)
1821 #define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU mBIT(27)
1822 #define VXGE_HAL_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED mBIT(31)
1843 #define VXGE_HAL_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR mBIT(63)
1847 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN mBIT(3)
1848 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP mBIT(7)
1849 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN mBIT(11)
1850 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP mBIT(15)
1851 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT mBIT(19)
1852 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK mBIT(23)
1853 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN mBIT(27)
1854 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP mBIT(31)
1855 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE mBIT(35)
1856 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV mBIT(39)
1857 #define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE mBIT(47)
1864 #define VXGE_HAL_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR mBIT(63)
1868 #define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN mBIT(3)
1869 #define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP mBIT(7)
1870 #define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN mBIT(11)
1871 #define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP mBIT(15)
1872 #define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT mBIT(19)
1873 #define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK mBIT(23)
1877 #define VXGE_HAL_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n) mBIT(n)
1881 #define VXGE_HAL_XGMAC_GEN_STATUS_XMACJ_NTWK_OK mBIT(3)
1882 #define VXGE_HAL_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE mBIT(11)
1892 #define VXGE_HAL_XGMAC_MAIN_CFG_PORT_PORT_EN mBIT(3)
1899 #define VXGE_HAL_XGMAC_STATUS_PORT_RMAC_REMOTE_FAULT mBIT(3)
1900 #define VXGE_HAL_XGMAC_STATUS_PORT_RMAC_LOCAL_FAULT mBIT(7)
1901 #define VXGE_HAL_XGMAC_STATUS_PORT_XMACJ_MAC_PHY_LAYER_AVAIL mBIT(11)
1902 #define VXGE_HAL_XGMAC_STATUS_PORT_XMACJ_PORT_OK mBIT(15)
1907 #define VXGE_HAL_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT mBIT(7)
1908 #define VXGE_HAL_XMAC_GEN_CFG_FAULT_BEHAVIOUR mBIT(27)
1912 #define VXGE_HAL_XMAC_TIMESTAMP_EN mBIT(3)
1915 #define VXGE_HAL_XMAC_TIMESTAMP_TIMER_RESTART mBIT(19)
1920 #define VXGE_HAL_XMAC_STATS_GEN_CFG_VLAN_HANDLING mBIT(15)
1923 #define VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE mBIT(15)
1931 #define VXGE_HAL_ASIC_NTWK_CTRL_REQ_TEST_NTWK mBIT(3)
1932 #define VXGE_HAL_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT mBIT(11)
1933 #define VXGE_HAL_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT mBIT(15)
1935 #define VXGE_HAL_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n) mBIT(n)
1937 #define VXGE_HAL_ASIC_NTWK_CFG_PORT_NUM_VP(n) mBIT(n)
1939 #define VXGE_HAL_XMAC_CFG_PORT_XGMII_LOOPBACK mBIT(3)
1940 #define VXGE_HAL_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK mBIT(7)
1941 #define VXGE_HAL_XMAC_CFG_PORT_XGMII_TX_BEHAV mBIT(11)
1942 #define VXGE_HAL_XMAC_CFG_PORT_XGMII_RX_BEHAV mBIT(15)
1946 #define VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_TX_ACT_PULSE_EXTEND mBIT(11)
1947 #define VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_RX_ACT_PULSE_EXTEND mBIT(15)
1948 #define VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_COMBINE_TXRX mBIT(35)
1952 #define VXGE_HAL_LAG_CFG_EN mBIT(3)
1954 #define VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV mBIT(11)
1955 #define VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV mBIT(15)
1956 #define VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM mBIT(19)
1958 #define VXGE_HAL_LAG_STATUS_XLCM_WAITING_TO_FAILBACK mBIT(3)
1961 #define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY mBIT(3)
1962 #define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES mBIT(7)
1963 #define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM mBIT(11)
1964 #define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK mBIT(15)
1965 #define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN mBIT(19)
1971 #define VXGE_HAL_LAG_LACP_CFG_EN mBIT(3)
1972 #define VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN mBIT(7)
1973 #define VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP mBIT(11)
1974 #define VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK mBIT(15)
1987 #define VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR mBIT(51)
1988 #define VXGE_HAL_LAG_SYS_ID_ADDR_SEL mBIT(55)
1995 #define VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR mBIT(51)
1996 #define VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL mBIT(55)
2003 #define VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR mBIT(19)
2012 #define VXGE_HAL_LAG_AGGR_STATE_LAGC_TX mBIT(3)
2013 #define VXGE_HAL_LAG_AGGR_STATE_LAGC_RX mBIT(7)
2014 #define VXGE_HAL_LAG_AGGR_STATE_LAGC_READY mBIT(11)
2015 #define VXGE_HAL_LAG_AGGR_STATE_LAGC_INDIVIDUAL mBIT(15)
2019 #define VXGE_HAL_LAG_PORT_CFG_EN mBIT(3)
2020 #define VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO mBIT(7)
2021 #define VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR mBIT(11)
2022 #define VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO mBIT(15)
2029 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY mBIT(3)
2030 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT mBIT(7)
2031 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION mBIT(11)
2032 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION mBIT(15)
2033 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING mBIT(19)
2034 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING mBIT(23)
2035 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED mBIT(27)
2036 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED mBIT(31)
2045 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY mBIT(3)
2046 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT mBIT(7)
2047 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION mBIT(11)
2048 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION mBIT(15)
2049 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING mBIT(19)
2050 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING mBIT(23)
2051 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED mBIT(27)
2052 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED mBIT(31)
2055 #define VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID mBIT(19)
2059 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY mBIT(3)
2060 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT mBIT(7)
2061 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION mBIT(11)
2062 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION mBIT(15)
2063 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING mBIT(19)
2064 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING mBIT(23)
2065 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED mBIT(27)
2066 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED mBIT(31)
2075 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY mBIT(3)
2076 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT mBIT(7)
2077 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION mBIT(11)
2078 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION mBIT(15)
2079 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING mBIT(19)
2080 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING mBIT(23)
2081 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED mBIT(27)
2082 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED mBIT(31)
2084 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_READY mBIT(3)
2086 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM mBIT(11)
2087 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED mBIT(15)
2088 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED mBIT(18)
2089 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED mBIT(19)
2090 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_NTT mBIT(23)
2091 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN mBIT(27)
2092 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN mBIT(31)
2093 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH mBIT(32)
2094 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH mBIT(33)
2095 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH mBIT(34)
2096 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH mBIT(35)
2100 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE mBIT(54)
2101 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE mBIT(55)
2124 #define VXGE_HAL_TRANSCEIVER_CTRL_PORT_TCVR_TX_ON mBIT(3)
2126 #define VXGE_HAL_ASIC_GPIO_CTRL_XMACJ_GPIO_DATA_IN(n) mBIT(n)
2127 #define VXGE_HAL_ASIC_GPIO_CTRL_GPIO_DATA_OUT(n) mBIT(n)
2128 #define VXGE_HAL_ASIC_GPIO_CTRL_GPIO_OUT_EN(n) mBIT(n)
2130 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_LINK_INVERT mBIT(3)
2131 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_10G_INVERT mBIT(7)
2132 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_TX_ACT_INVERT mBIT(11)
2133 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_RX_ACT_INVERT mBIT(15)
2134 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_LINK_INVERT mBIT(19)
2135 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_10G_INVERT mBIT(23)
2136 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_TX_ACT_INVERT mBIT(27)
2137 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_RX_ACT_INVERT mBIT(31)
2138 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_AUX_LED1_INVERT mBIT(35)
2139 #define VXGE_HAL_ASIC_LED_BEACON_CTRL_AUX_LED2_INVERT mBIT(39)
2141 #define VXGE_HAL_ASIC_LED_CTRL0_PORT0_LINK_ON mBIT(3)
2142 #define VXGE_HAL_ASIC_LED_CTRL0_PORT0_10G_ON mBIT(7)
2143 #define VXGE_HAL_ASIC_LED_CTRL0_PORT1_LINK_ON mBIT(19)
2144 #define VXGE_HAL_ASIC_LED_CTRL0_PORT1_10G_ON mBIT(23)
2145 #define VXGE_HAL_ASIC_LED_CTRL0_AUX_LED1_ON mBIT(35)
2146 #define VXGE_HAL_ASIC_LED_CTRL0_AUX_LED2_ON mBIT(39)
2152 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_PULSE_EXTEND mBIT(19)
2153 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_PULSE_EXTEND mBIT(23)
2154 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_PULSE_EXTEND mBIT(27)
2155 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_PULSE_EXTEND mBIT(31)
2172 #define VXGE_HAL_USDC_SGRP_PARTITION_ENABLE mBIT(7)
2387 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_0_ERR mBIT(0)
2388 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_1_ERR mBIT(1)
2389 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_2_ERR mBIT(2)
2390 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_3_ERR mBIT(3)
2391 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_4_ERR mBIT(4)
2392 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_5_ERR mBIT(5)
2393 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_6_ERR mBIT(6)
2394 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_7_ERR mBIT(7)
2395 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_8_ERR mBIT(8)
2396 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_9_ERR mBIT(9)
2397 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_10_ERR mBIT(10)
2398 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_11_ERR mBIT(11)
2399 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_12_ERR mBIT(12)
2400 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_13_ERR mBIT(13)
2401 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_14_ERR mBIT(14)
2402 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_15_ERR mBIT(15)
2403 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_16_ERR mBIT(16)
2404 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_17_ERR mBIT(17)
2405 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_18_ERR mBIT(18)
2406 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_19_ERR mBIT(19)
2407 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_20_ERR mBIT(20)
2408 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_21_ERR mBIT(21)
2409 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_22_ERR mBIT(22)
2410 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_23_ERR mBIT(23)
2411 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_24_ERR mBIT(24)
2412 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_25_ERR mBIT(25)
2413 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_26_ERR mBIT(26)
2414 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_27_ERR mBIT(27)
2415 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_28_ERR mBIT(28)
2416 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_29_ERR mBIT(29)
2417 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_30_ERR mBIT(30)
2418 #define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_31_ERR mBIT(31)
2422 #define VXGE_HAL_USDC_READ_CNTRL_USDC_FREEZE mBIT(7)
2424 #define VXGE_HAL_USDC_READ_CNTRL_USDC_WORD_SEL mBIT(23)
2777 #define VXGE_HAL_USDC_ECC_CTRL_ECC_DISABLE mBIT(7)
2779 #define VXGE_HAL_USDC_VPBP_CTRL_MSG_DIS mBIT(0)
2780 #define VXGE_HAL_USDC_VPBP_CTRL_H2L_DIS mBIT(1)
2784 #define VXGE_HAL_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT mBIT(1)
2785 #define VXGE_HAL_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT mBIT(2)
2786 #define VXGE_HAL_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT mBIT(4)
2787 #define VXGE_HAL_RTDMA_INT_STATUS_SM_ERROR_SM_INT mBIT(5)
2790 #define VXGE_HAL_PDA_ALARM_REG_PDA_HSC_FIFO_ERR mBIT(0)
2791 #define VXGE_HAL_PDA_ALARM_REG_PDA_SM_ERR mBIT(1)
2795 #define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n) mBIT(n)
2796 #define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n) mBIT(n)
2797 #define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n) mBIT(n)
2798 #define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n) mBIT(n)
2799 #define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n) mBIT(n)
2800 #define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_SERR(n) mBIT(n)
2804 #define VXGE_HAL_LSO_ERROR_REG_PCC_LSO_ABORT(n) mBIT(n)
2805 #define VXGE_HAL_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n) mBIT(n)
2809 #define VXGE_HAL_SM_ERROR_REG_SM_FSM_ERR_ALARM mBIT(15)
2813 #define VXGE_HAL_PDA_CONTROL_PCC_INTERLOCK_EN mBIT(7)
2814 #define VXGE_HAL_PDA_CONTROL_SPLIT_IDLE mBIT(15)
2815 #define VXGE_HAL_PDA_CONTROL_PCC_MAX_DISABLE mBIT(23)
2816 #define VXGE_HAL_PDA_CONTROL_H2L_DO_GATE_EN mBIT(31)
2817 #define VXGE_HAL_PDA_CONTROL_TXD_INT_NUM_CTLR mBIT(39)
2818 #define VXGE_HAL_PDA_CONTROL_ISSUE_8B_READ mBIT(47)
2854 #define VXGE_HAL_PDA_VP_RD_XON_ENABLE mBIT(0)
2855 #define VXGE_HAL_PDA_VP_WR_XON_ENABLE mBIT(1)
2856 #define VXGE_HAL_PDA_VP_NO_ACTIVITY_DISABLE mBIT(2)
2858 #define VXGE_HAL_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP mBIT(7)
2860 #define VXGE_HAL_PCC_CFG_PCC_ENABLE(n) mBIT(n)
2861 #define VXGE_HAL_PCC_CFG_PCC_ECC_ENABLE_N(n) mBIT(n)
2864 #define VXGE_HAL_PCC_CONTROL_EARLY_ASSIGN_EN mBIT(15)
2865 #define VXGE_HAL_PCC_CONTROL_UNBLOCK_DB_ERR mBIT(31)
2880 #define VXGE_HAL_G3CMCT_INT_STATUS_ERR_G3IF_INT mBIT(0)
2883 #define VXGE_HAL_G3CMCT_ERR_REG_G3IF_SM_ERR mBIT(4)
2884 #define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_DECC mBIT(5)
2885 #define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC mBIT(6)
2886 #define VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC mBIT(7)
2887 #define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_SECC mBIT(29)
2888 #define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC mBIT(30)
2889 #define VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC mBIT(31)
2902 #define VXGE_HAL_G3CMCT_CONFIG1_BIC_OFF mBIT(15)
2903 #define VXGE_HAL_G3CMCT_CONFIG1_IGNORE_BEM mBIT(23)
2905 #define VXGE_HAL_G3CMCT_CONFIG1_CMD_START_PHASE mBIT(39)
2913 #define VXGE_HAL_G3CMCT_CONFIG2_DEFINE_CAD mBIT(31)
2914 #define VXGE_HAL_G3CMCT_CONFIG2_DEFINE_NOP_AD mBIT(39)
2919 #define VXGE_HAL_G3CMCT_INIT0_MRS_DLL mBIT(23)
2920 #define VXGE_HAL_G3CMCT_INIT0_MRS_TM mBIT(39)
2922 #define VXGE_HAL_G3CMCT_INIT0_MRS_BT mBIT(55)
2926 #define VXGE_HAL_G3CMCT_INIT1_EMRS_AD_TER mBIT(15)
2927 #define VXGE_HAL_G3CMCT_INIT1_EMRS_ID mBIT(23)
2928 #define VXGE_HAL_G3CMCT_INIT1_EMRS_RON mBIT(39)
2929 #define VXGE_HAL_G3CMCT_INIT1_EMRS_AL mBIT(47)
2934 #define VXGE_HAL_G3CMCT_INIT2_START_INI mBIT(15)
2949 #define VXGE_HAL_G3CMCT_INIT4_CKE_INIT_VAL mBIT(31)
2952 #define VXGE_HAL_G3CMCT_INIT4_ICTRL_INIT_DONE mBIT(55)
2953 #define VXGE_HAL_G3CMCT_INIT4_IOCAL_WAIT_DISABLE mBIT(63)
3007 #define VXGE_HAL_G3CMCT_TEST01_TEST_MODE mBIT(23)
3008 #define VXGE_HAL_G3CMCT_TEST01_TEST_GO mBIT(31)
3009 #define VXGE_HAL_G3CMCT_TEST01_TEST_DONE mBIT(39)
3011 #define VXGE_HAL_G3CMCT_TEST01_TEST_DATA_ADDR mBIT(63)
3048 #define VXGE_HAL_G3CMCT_INIT41_ENABLE_CMU mBIT(15)
3088 #define VXGE_HAL_G3CMCT_LOOP_BACK_MODE mBIT(39)
3089 #define VXGE_HAL_G3CMCT_LOOP_BACK_GO mBIT(47)
3090 #define VXGE_HAL_G3CMCT_LOOP_BACK_DONE mBIT(55)
3145 #define VXGE_HAL_G3CMCT_TRAN_AP_CNT_UPDATE mBIT(39)
3147 #define VXGE_HAL_G3CMCT_G3BIST_DISABLE_MAIN mBIT(7)
3148 #define VXGE_HAL_G3CMCT_G3BIST_DISABLE_ICTRL mBIT(15)
3154 #define VXGE_HAL_MC_INT_STATUS_MC_ERR_MC_INT mBIT(3)
3155 #define VXGE_HAL_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT mBIT(7)
3156 #define VXGE_HAL_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT mBIT(11)
3157 #define VXGE_HAL_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT mBIT(15)
3160 #define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A mBIT(3)
3161 #define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B mBIT(4)
3162 #define VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR mBIT(5)
3163 #define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0 mBIT(6)
3164 #define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1 mBIT(7)
3165 #define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A mBIT(10)
3166 #define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B mBIT(11)
3167 #define VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR mBIT(12)
3168 #define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 mBIT(13)
3169 #define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 mBIT(14)
3170 #define VXGE_HAL_MC_ERR_REG_MC_SM_ERR mBIT(15)
3174 #define VXGE_HAL_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR mBIT(3)
3175 #define VXGE_HAL_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR mBIT(7)
3187 #define VXGE_HAL_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN mBIT(62)
3188 #define VXGE_HAL_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ mBIT(63)
3269 #define VXGE_HAL_RX_QUEUE_CFG_QUEUE_SIZE_ENABLE mBIT(39)
3400 #define VXGE_HAL_TRAFFIC_CTRL_BLOCK_ING_PATH mBIT(7)
3401 #define VXGE_HAL_TRAFFIC_CTRL_BLOCK_EGR_PATH mBIT(15)
3406 #define VXGE_HAL_XFMD_ARB_CTRL_ISTAGE_MASK mBIT(7)
3432 #define VXGE_HAL_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT mBIT(3)
3433 #define VXGE_HAL_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT mBIT(7)
3434 #define VXGE_HAL_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT mBIT(11)
3435 #define VXGE_HAL_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT mBIT(15)
3436 #define VXGE_HAL_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT mBIT(19)
3439 #define VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR mBIT(3)
3440 #define VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR mBIT(7)
3441 #define VXGE_HAL_DBECC_ERR_REG_PCI_P_HDR_DB_ERR mBIT(11)
3442 #define VXGE_HAL_DBECC_ERR_REG_PCI_P_DATA_DB_ERR mBIT(15)
3443 #define VXGE_HAL_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR mBIT(19)
3444 #define VXGE_HAL_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR mBIT(23)
3448 #define VXGE_HAL_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR mBIT(3)
3449 #define VXGE_HAL_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR mBIT(7)
3450 #define VXGE_HAL_SBECC_ERR_REG_PCI_P_HDR_SG_ERR mBIT(11)
3451 #define VXGE_HAL_SBECC_ERR_REG_PCI_P_DATA_SG_ERR mBIT(15)
3452 #define VXGE_HAL_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR mBIT(19)
3453 #define VXGE_HAL_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR mBIT(23)
3457 #define VXGE_HAL_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG mBIT(3)
3458 #define VXGE_HAL_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG mBIT(7)
3459 #define VXGE_HAL_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR mBIT(11)
3460 #define VXGE_HAL_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE mBIT(15)
3461 #define VXGE_HAL_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET mBIT(19)
3462 #define VXGE_HAL_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET mBIT(23)
3463 #define VXGE_HAL_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP mBIT(27)
3467 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT mBIT(0)
3468 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT mBIT(1)
3469 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT mBIT(2)
3470 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT mBIT(3)
3471 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT mBIT(4)
3472 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT mBIT(5)
3473 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT mBIT(6)
3474 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT mBIT(7)
3475 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT mBIT(8)
3476 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT mBIT(9)
3477 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT mBIT(10)
3478 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT mBIT(11)
3479 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT mBIT(12)
3480 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT mBIT(13)
3481 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT mBIT(14)
3482 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT mBIT(15)
3483 #define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT mBIT(16)
3489 #define VXGE_HAL_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT mBIT(0)
3490 #define VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT mBIT(1)
3491 #define VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT mBIT(2)
3492 #define VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT mBIT(3)
3493 #define VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT mBIT(4)
3494 #define VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT mBIT(5)
3495 #define VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT mBIT(6)
3496 #define VXGE_HAL_GCMG1_INT_STATUS_UQM_ERR_UQM_INT mBIT(7)
3497 #define VXGE_HAL_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT mBIT(8)
3502 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_OVERLAPPING_SYNC_ERR mBIT(23)
3505 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2STE_UFLOW_ERR mBIT(55)
3506 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2TTE_UFLOW_ERR mBIT(63)
3521 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_DB_ERR mBIT(0)
3522 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_SCREQ_ERR mBIT(1)
3523 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_OFLOW_ERR mBIT(2)
3524 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_R_WN_ERR mBIT(3)
3525 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_UFLOW_ERR mBIT(4)
3526 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_OFLOW_ERR mBIT(5)
3527 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_UFLOW_ERR mBIT(6)
3528 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_OFLOW_ERR mBIT(7)
3529 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_UFLOW_ERR mBIT(8)
3530 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_OFLOW_ERR mBIT(9)
3531 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_UFLOW_ERR mBIT(10)
3532 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_OFLOW_ERR mBIT(11)
3533 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_R_WN_ERR mBIT(12)
3534 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_UFLOW_ERR mBIT(13)
3535 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_OFLOW_ERR mBIT(14)
3536 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_UFLOW_ERR mBIT(15)
3537 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_OFLOW_ERR mBIT(16)
3538 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_R_WN_ERR mBIT(17)
3539 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_UFLOW_ERR mBIT(18)
3540 #define VXGE_HAL_GSSC_ERR1_REG_SSCC_SCRESP_ERR mBIT(19)
3548 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCMREQCMD_FIFO_ERR mBIT(16)
3549 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCMREQDAT_FIFO_ERR mBIT(17)
3550 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM_CAM_FIFO_PUSH_ERR mBIT(18)
3551 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM_CAM_EIP_FIFO_PUSH_ERR mBIT(19)
3552 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM2CMA_FIFO_POP_ERR mBIT(20)
3553 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM_CAM_FIFO_PUSH_ERR mBIT(24)
3554 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM_CAM_EIP_FIFO_PUSH_ERR mBIT(25)
3555 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM2CMA_LP_FIFO_POP_ERR mBIT(26)
3556 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM2CMA_HP_FIFO_POP_ERR mBIT(27)
3557 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_WSE2CMA_FIFO_POP_ERR mBIT(28)
3558 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_RRP2CMA_LP_FIFO_POP_ERR mBIT(29)
3559 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_RRP2CMA_HP_FIFO_POP_ERR mBIT(30)
3560 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_IPWOGRRESP_FIFO_POP_ERR mBIT(31)
3561 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPRPEDAT_FIFO_ERR mBIT(32)
3562 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPWRRESP_FIFO_PUSH_ERR mBIT(33)
3563 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPCMCREQCMD_ERR mBIT(34)
3564 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_HPCMCREQCMD_ERR mBIT(35)
3565 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMCREQDAT_ERR mBIT(36)
3566 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CMR_SM_ERR mBIT(41)
3567 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CAR_SM_ERR mBIT(42)
3568 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_HCMR_SM_ERR mBIT(43)
3569 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_LCMR_SM_ERR mBIT(44)
3570 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_CAR_SM_ERR mBIT(45)
3571 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CMR_INFO_ERR mBIT(55)
3572 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_WSE_WQE_RD_ERR mBIT(56)
3573 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2WGM_NEXT_WQE_PTR_ERR mBIT(57)
3574 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2RLM_RMV_DATA_ERR mBIT(58)
3575 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2DLM_RMV_DATA_ERR mBIT(59)
3576 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2ELM_RMV_DATA_ERR mBIT(60)
3577 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2CGM_CQEGRP_ROW_DATA_ERR mBIT(61)
3578 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2RLM_RMV_DATA_ERR mBIT(62)
3579 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2ELM_RMV_DATA_ERR mBIT(63)
3583 #define VXGE_HAL_UQM_ERR_REG_UQM_UQM_CMCREQ_ECC_SG_ERR mBIT(0)
3584 #define VXGE_HAL_UQM_ERR_REG_UQM_UQM_CMCREQ_ECC_DB_ERR mBIT(1)
3585 #define VXGE_HAL_UQM_ERR_REG_UQM_UQM_SM_ERR mBIT(8)
3592 #define VXGE_HAL_SSCC_CONFIG_ALLOW_NOTFOUND_CACHING mBIT(39)
3595 #define VXGE_HAL_SSCC_CONFIG_NULL_LOOKUP mBIT(63)
3612 #define VXGE_HAL_GCMG1_ECC_ENABLE_SSCC_N mBIT(7)
3613 #define VXGE_HAL_GCMG1_ECC_ENABLE_UQM_N mBIT(15)
3614 #define VXGE_HAL_GCMG1_ECC_ENABLE_QCC_N mBIT(23)
3618 #define VXGE_HAL_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT mBIT(0)
3619 #define VXGE_HAL_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT mBIT(1)
3620 #define VXGE_HAL_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT mBIT(2)
3621 #define VXGE_HAL_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT mBIT(3)
3624 #define VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2STE_OFLOW_ERR mBIT(0)
3625 #define VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2TTE_OFLOW_ERR mBIT(1)
3629 #define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_MAX_WQE_GRP_INFO_ERR mBIT(0)
3630 #define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_WQE_FREE_LIST_EMPTY_INFO_ERR mBIT(1)
3631 #define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_FLM_WQE_ID_FIFO_ERR mBIT(2)
3632 #define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_CACHE_FULL_INFO_ERR mBIT(3)
3633 #define VXGE_HAL_PQCC_ERR_REG_QCC_QCC_PDA_ARB_SM_ERR mBIT(32)
3634 #define VXGE_HAL_PQCC_ERR_REG_QCC_QCC_CP_ARB_SM_ERR mBIT(33)
3635 #define VXGE_HAL_PQCC_ERR_REG_QCC_QCC_CXP2QCC_FIFO_ERR mBIT(63)
3640 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_DMACQERSP_SG_ERR mBIT(4)
3642 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_DMACQERSP_DB_ER mBIT(12)
3643 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_RMW_FIFO_ERR mBIT(16)
3644 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_FIFO_ERR mBIT(17)
3645 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_CAM_FIFO_POP_ERR mBIT(18)
3646 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_CAM_EIP_FIFO_POP_ERR mBIT(19)
3647 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM2CMA_FIFO_PUSH_ERR mBIT(20)
3648 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_HPRPEREQ_FIFO_ERR mBIT(21)
3649 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_LPRPEREQ_FIFO_ERR mBIT(22)
3650 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_LPRPERSP_FIFO_ERR mBIT(23)
3651 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_USDC_DBELL_FIFO_ERR mBIT(24)
3652 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CXP_MSG_IN_FIFO_ERR mBIT(25)
3653 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CXP_MSG_OUT_FIFO_ERR mBIT(26)
3654 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_FIFO_ERR mBIT(27)
3655 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CGM_CCM_REQ_FIFO_ERR mBIT(28)
3656 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_EXCESSIVE_RD_RESP_ERR mBIT(29)
3657 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CDR_SERR mBIT(32)
3658 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_FLM_SM_ERR mBIT(33)
3659 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_CRP_SM_ERR mBIT(34)
3660 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_ARB_SM_ERR mBIT(35)
3661 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_RCL_SM_ERR mBIT(36)
3662 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CIN_SM_ERR mBIT(37)
3663 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CSE_SM_ERR mBIT(38)
3664 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_SM_ERR mBIT(39)
3665 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_SM_ERR mBIT(40)
3666 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_ADD_SM_ERR mBIT(41)
3667 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_SM_ERR mBIT(42)
3668 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_ADD_SM_ERR mBIT(43)
3669 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_FULL_INFO_ERR mBIT(58)
3670 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_MAX_CQE_GRP_INFO_ERR mBIT(59)
3671 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CDR_SM_INFO_ERR mBIT(60)
3672 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_BAD_CIN_INFO_ERR mBIT(61)
3673 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_NO_CQE_GRP_INFO_ERR mBIT(62)
3674 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_BAD_VPIN_INFO_ERR mBIT(63)
3680 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_DMAWQERSP_SG_ERR mBIT(8)
3681 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RPEREQDAT_SG_ERR mBIT(9)
3682 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_BAD_VPIN_INFO_ERR mBIT(10)
3683 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WDR_SM_INFO_ERR mBIT(11)
3684 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_BAD_SIN_INFO_ERR mBIT(12)
3685 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_EXCESSIVE_RD_RESP_ERR mBIT(13)
3686 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_DMAWQERSP_DB_ERR mBIT(14)
3687 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RPEREQDAT_DB_ERR mBIT(15)
3690 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_FIFO_ERR mBIT(24)
3691 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_CAM_FIFO_POP_ERR mBIT(25)
3692 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_CAM_EIP_FIFO_POP_ERR mBIT(26)
3693 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM2CMA_LP_FIFO_PUSH_ERR mBIT(27)
3694 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM2CMA_HP_FIFO_PUSH_ERR mBIT(28)
3695 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WSE2CMA_FIFO_PUSH_ERR mBIT(29)
3696 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP2CMA_LP_FIFO_PUSH_ERR mBIT(30)
3697 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP2CMA_HP_FIFO_PUSH_ERR mBIT(31)
3698 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_HPRPEREQ_FIFO_ERR mBIT(32)
3699 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_IPWOGRREQSB_FIFO_ERR mBIT(33)
3700 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_IPWOGRRESP_FIFO_POP_ERR mBIT(34)
3701 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_FIFO_ERR mBIT(35)
3702 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEREQ_FIFO_ERR mBIT(36)
3703 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPERESP_FIFO_ERR mBIT(37)
3704 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPERESPSB_FIFO_ERR mBIT(38)
3705 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPWRREQSB_FIFO_ERR mBIT(39)
3706 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPWRRESP_FIFO_POP_ERR mBIT(40)
3707 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_SWRRESP_FIFO_ERR mBIT(41)
3708 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_RPE_REQ_FIFO_ERR mBIT(42)
3709 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_RPE_LASTOD_FIFO_ERR mBIT(43)
3710 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_USDC_DBELL_FIFO_ERR mBIT(44)
3711 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CXP_MSG_IN_FIFO_ERR mBIT(45)
3712 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CXP_MSG_OUT_FIFO_ERR mBIT(46)
3713 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_RMW_FIFO_ERR mBIT(47)
3714 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_FIFO_ERR mBIT(48)
3715 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_FIFO_ERR mBIT(49)
3716 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP_RESPDATA_ARB_SM_ERR mBIT(50)
3717 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WDR_SERR mBIT(51)
3718 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMA_RLP_SM_ERR mBIT(52)
3719 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_FLM_SM_ERR mBIT(53)
3720 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_RCL_SM_ERR mBIT(54)
3721 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CIN_SM_ERR mBIT(55)
3722 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WSE_SM_ERR mBIT(56)
3723 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_SM_ERR mBIT(57)
3724 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_SM_ERR mBIT(58)
3725 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_ADD_SM_ERR mBIT(59)
3726 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_SM_ERR mBIT(60)
3727 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_ADD_SM_ERR mBIT(61)
3728 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_SM_ERR mBIT(62)
3729 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_ADD_SM_ERR mBIT(63)
3735 #define VXGE_HAL_QCC_SRQ_CQRQ_CONSERVATIVE_SM_CRD_RTN mBIT(47)
3741 #define VXGE_HAL_QCC_BP_CTRL_RD_XON mBIT(7)
3743 #define VXGE_HAL_PCMG1_ECC_ENABLE_QCC_N mBIT(23)
3760 #define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_NO_WQE_OD_GRP_AVAIL mBIT(0)
3768 #define VXGE_HAL_ONE_INT_STATUS_RXPE_ERR_RXPE_INT mBIT(7)
3770 mBIT(13)
3772 mBIT(14)
3773 #define VXGE_HAL_ONE_INT_STATUS_TXPE_ERR_TXPE_INT mBIT(15)
3774 #define VXGE_HAL_ONE_INT_STATUS_DLM_ERR_DLM_INT mBIT(23)
3775 #define VXGE_HAL_ONE_INT_STATUS_PE_ERR_PE_INT mBIT(31)
3776 #define VXGE_HAL_ONE_INT_STATUS_RPE_ERR_RPE_INT mBIT(39)
3777 #define VXGE_HAL_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT mBIT(47)
3778 #define VXGE_HAL_ONE_INT_STATUS_OES_ERR_OES_INT mBIT(55)
3783 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_DB_ERR mBIT(8)
3784 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_DB_ERR mBIT(9)
3785 #define VXGE_HAL_RPE_ERR_REG_RPE_RCQ_DB_ERR mBIT(10)
3786 #define VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_DB_ERR mBIT(11)
3789 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_SG_ERR mBIT(24)
3790 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_SG_ERR mBIT(25)
3791 #define VXGE_HAL_RPE_ERR_REG_RPE_RCQ_SG_ERR mBIT(26)
3792 #define VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_SG_ERR mBIT(27)
3793 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CTXTRDRQ_FIFO_ERR mBIT(32)
3794 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CTXTWRRQ_FIFO_ERR mBIT(33)
3795 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQRQLDRQ_FIFO_ERR mBIT(34)
3796 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_SRQLDRQ_FIFO_ERR mBIT(35)
3797 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQERDRQ_FIFO_ERR mBIT(36)
3798 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQEWRRQ_FIFO_ERR mBIT(37)
3799 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQEAVAILRQ_FIFO_ERR mBIT(38)
3800 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQECOMPL_FIFO_ERR mBIT(39)
3801 #define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQEADDRRQ_FIFO_ERR mBIT(40)
3802 #define VXGE_HAL_RPE_ERR_REG_RPE_RCC_CTXTLDNT_FIFO_ERR mBIT(41)
3803 #define VXGE_HAL_RPE_ERR_REG_RPE_RCC_RCCRESP_FIFO_ERR mBIT(42)
3804 #define VXGE_HAL_RPE_ERR_REG_RPE_QEM_OESPREINIT_FIFO_ERR mBIT(43)
3805 #define VXGE_HAL_RPE_ERR_REG_RPE_QEM_EVENT_FIFO_ERR mBIT(44)
3806 #define VXGE_HAL_RPE_ERR_REG_RPE_QEM_WQELDNT_FIFO_ERR mBIT(45)
3807 #define VXGE_HAL_RPE_ERR_REG_RPE_QEM_QEMRESP_FIFO_ERR mBIT(46)
3808 #define VXGE_HAL_RPE_ERR_REG_RPE_QEM_PDM_CMD_FIFO_ERR mBIT(47)
3809 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_CMDRESP_FIFO_ERR mBIT(48)
3810 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_FIFO_ERR mBIT(49)
3811 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_EPE_SPQ_FIFO_ERR mBIT(50)
3812 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_EPE_STCRESP_FIFO_ERR mBIT(51)
3813 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RIM_RIMIPB_FIFO_ERR mBIT(52)
3814 #define VXGE_HAL_RPE_ERR_REG_RPE_RCI_MCQLEN_FIFO_ERR mBIT(53)
3815 #define VXGE_HAL_RPE_ERR_REG_RPE_RCI_PCQLEN_FIFO_ERR mBIT(54)
3816 #define VXGE_HAL_RPE_ERR_REG_RPE_RCI_RDLIM_FIFO_ERR mBIT(55)
3817 #define VXGE_HAL_RPE_ERR_REG_RPE_MSG_RCMD_FIFO_ERR mBIT(56)
3818 #define VXGE_HAL_RPE_ERR_REG_RPE_DLM_RCMD_FIFO_ERR mBIT(57)
3819 #define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_FIFO_ERR mBIT(58)
3820 #define VXGE_HAL_RPE_ERR_REG_RPE_RCQ_FIFO_ERR mBIT(59)
3821 #define VXGE_HAL_RPE_ERR_REG_RPE_RCO_CQE_FIFO_ERR mBIT(60)
3822 #define VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_FIFO_ERR mBIT(61)
3826 #define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PA_SG_ERR mBIT(0)
3827 #define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PB_SG_ERR mBIT(1)
3828 #define VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_SG_ERR mBIT(2)
3829 #define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_RDFIFO_STATE_SM_ERR mBIT(8)
3830 #define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_STATE_SM_ERR mBIT(9)
3831 #define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTWRQ_ADDR_STATE_SM_ERR mBIT(10)
3832 #define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTWRQ_DATA_STATE_SM_ERR mBIT(11)
3833 #define VXGE_HAL_PE_ERR_REG_PE_CDP_DLM_CTXT_STATE_SM_ERR mBIT(12)
3834 #define VXGE_HAL_PE_ERR_REG_PE_CDP_RDMEM_ADDR_STATE_SM_ERR mBIT(13)
3835 #define VXGE_HAL_PE_ERR_REG_PE_CDP_RDMEM_DATA_STATE_SM_ERR mBIT(14)
3836 #define VXGE_HAL_PE_ERR_REG_PE_CDP_RDRESP_STATE_SM_ERR mBIT(15)
3837 #define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_RDCTXT_DATA_STATE_SM_ERR mBIT(16)
3838 #define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPEIF_STATE_SM_ERR mBIT(17)
3839 #define VXGE_HAL_PE_ERR_REG_PE_CDP_TCM_CTXT_STATE_SM_ERR mBIT(18)
3840 #define VXGE_HAL_PE_ERR_REG_PE_SCC_CTXT_CNTRL_SM_ERR mBIT(19)
3841 #define VXGE_HAL_PE_ERR_REG_PE_SCC_RECALL_SM_ERR mBIT(20)
3842 #define VXGE_HAL_PE_ERR_REG_PE_SCC_NCE_FETCH_STATE_SM_ERR mBIT(21)
3843 #define VXGE_HAL_PE_ERR_REG_PE_NCC_NCE_CNTRL_SM_ERR mBIT(22)
3844 #define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_MEMCNTRL_STATE_SM_ERR mBIT(23)
3845 #define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NRRQ_RDFIFO_STATE_SM_ERR mBIT(24)
3846 #define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NRRQ_STATE_SM_ERR mBIT(25)
3847 #define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NWRQ_RDFIFO_STATE_SM_ERR mBIT(26)
3848 #define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_RDMEM_DATA_STATE_SM_ERR mBIT(27)
3849 #define VXGE_HAL_PE_ERR_REG_PE_CMGIF_HDREQ_ARB_STATE_SM_ERR mBIT(28)
3850 #define VXGE_HAL_PE_ERR_REG_PE_CMGIF_HNREQ_ARB_STATE_SM_ERR mBIT(29)
3851 #define VXGE_HAL_PE_ERR_REG_PE_CMGIF_LDREQ_ARB_STATE_SM_ERR mBIT(30)
3852 #define VXGE_HAL_PE_ERR_REG_PE_CMGIF_LNREQ_ARB_STATE_SM_ERR mBIT(31)
3853 #define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_FIFO_ERR mBIT(32)
3854 #define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXT_FIFO_ERR mBIT(33)
3855 #define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_CTXT_WR_PHASE_ERR mBIT(34)
3856 #define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_CTXT_RD_PHASE_ERR mBIT(35)
3857 #define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_RD_RESP_PHASE_ERR mBIT(36)
3858 #define VXGE_HAL_PE_ERR_REG_PE_NDP_NRRQ_FIFO_ERR mBIT(37)
3859 #define VXGE_HAL_PE_ERR_REG_PE_NDP_NWRQ_FIFO_ERR mBIT(38)
3860 #define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_WRMEM_PHASE_ERR mBIT(39)
3861 #define VXGE_HAL_PE_ERR_REG_PE_NCC_PE_RESP_CMD_PHASE_ERR mBIT(40)
3862 #define VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_SM_ERR mBIT(48)
3863 #define VXGE_HAL_PE_ERR_REG_PE_PET_MEM_ARB_ERR mBIT(49)
3864 #define VXGE_HAL_PE_ERR_REG_PE_PET_UPDATE_FSM_ERR mBIT(50)
3865 #define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PA_DB_ERR mBIT(61)
3866 #define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PB_DB_ERR mBIT(62)
3867 #define VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_DB_ERR mBIT(63)
3871 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_FRM_SG_ERR mBIT(0)
3872 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_FRM_SG_ERR mBIT(1)
3873 #define VXGE_HAL_RXPE_ERR_REG_RXPE_FPDU_MEM_SG_ERR mBIT(2)
3879 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_TRCE_SG_ERR mBIT(13)
3880 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_TRCE_SG_ERR mBIT(14)
3881 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_FRM_DB_ERR mBIT(32)
3882 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_FRM_DB_ERR mBIT(33)
3883 #define VXGE_HAL_RXPE_ERR_REG_RXPE_FPDU_MEM_DB_ERR mBIT(34)
3889 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_TRCE_DB_ERR mBIT(45)
3890 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_TRCE_DB_ERR mBIT(46)
3891 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_XLMI_SERR mBIT(54)
3892 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_XLMI_SERR mBIT(55)
3893 #define VXGE_HAL_RXPE_ERR_REG_RXPE_DRAM_WR_ERR mBIT(58)
3894 #define VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGIN_WR_FSM_ERR mBIT(59)
3895 #define VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGIN_EVCTRL_FSM_ERR mBIT(60)
3896 #define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_FIFO_ERR mBIT(61)
3897 #define VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGOUT_COLLISION_ERR mBIT(62)
3898 #define VXGE_HAL_RXPE_ERR_REG_RXPE_SM_ERR mBIT(63)
3902 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PA_SG_ERR mBIT(0)
3903 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PB_SG_ERR mBIT(1)
3904 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PA_SG_ERR mBIT(2)
3905 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PB_SG_ERR mBIT(3)
3906 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PA_SG_ERR mBIT(4)
3907 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PB_SG_ERR mBIT(5)
3908 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_AWRQ_MEM_SG_ERR mBIT(6)
3909 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_LWRQ_MEM_SG_ERR mBIT(7)
3910 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PA_DB_ERR mBIT(8)
3911 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PB_DB_ERR mBIT(9)
3912 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PA_DB_ERR mBIT(10)
3913 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PB_DB_ERR mBIT(11)
3914 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PA_DB_ERR mBIT(12)
3915 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PB_DB_ERR mBIT(13)
3916 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_AWRQ_MEM_DB_ERR mBIT(14)
3917 #define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_LWRQ_MEM_DB_ERR mBIT(15)
3918 #define VXGE_HAL_DLM_ERR_REG_DLM_ACC_PA_STATE_SM_ERR mBIT(16)
3919 #define VXGE_HAL_DLM_ERR_REG_DLM_ACC_PB_STATE_SM_ERR mBIT(17)
3920 #define VXGE_HAL_DLM_ERR_REG_DLM_ACK_RDMEM_DATA_STATE_SM_ERR mBIT(18)
3921 #define VXGE_HAL_DLM_ERR_REG_DLM_AFLM_RDFIFO_STATE_SM_ERR mBIT(19)
3922 #define VXGE_HAL_DLM_ERR_REG_DLM_AFLM_STATE_SM_ERR mBIT(20)
3923 #define VXGE_HAL_DLM_ERR_REG_DLM_APTR_ALLOC_STATE_SM_ERR mBIT(21)
3924 #define VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_RDFIFO_STATE_SM_ERR mBIT(22)
3925 #define VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_STATE_SM_ERR mBIT(23)
3926 #define VXGE_HAL_DLM_ERR_REG_DLM_AWRQ_STATE_SM_ERR mBIT(24)
3927 #define VXGE_HAL_DLM_ERR_REG_DLM_EVENT_CTXT_STATE_SM_ERR mBIT(25)
3928 #define VXGE_HAL_DLM_ERR_REG_DLM_LCC_PA_STATE_SM_ERR mBIT(26)
3929 #define VXGE_HAL_DLM_ERR_REG_DLM_LCC_PB_STATE_SM_ERR mBIT(27)
3930 #define VXGE_HAL_DLM_ERR_REG_DLM_LFLM_RDFIFO_STATE_SM_ERR mBIT(28)
3931 #define VXGE_HAL_DLM_ERR_REG_DLM_LFLM_STATE_SM_ERR mBIT(29)
3932 #define VXGE_HAL_DLM_ERR_REG_DLM_LPTR_ALLOC_STATE_SM_ERR mBIT(30)
3933 #define VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_RDFIFO_STATE_SM_ERR mBIT(31)
3934 #define VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_STATE_SM_ERR mBIT(32)
3935 #define VXGE_HAL_DLM_ERR_REG_DLM_LWRQ_STATE_SM_ERR mBIT(33)
3936 #define VXGE_HAL_DLM_ERR_REG_DLM_PCIWR_STATE_SM_ERR mBIT(34)
3937 #define VXGE_HAL_DLM_ERR_REG_DLM_PFETCH_STATE_SM_ERR mBIT(35)
3938 #define VXGE_HAL_DLM_ERR_REG_DLM_RCC_PA_STATE_SM_ERR mBIT(36)
3939 #define VXGE_HAL_DLM_ERR_REG_DLM_RCC_PB_STATE_SM_ERR mBIT(37)
3940 #define VXGE_HAL_DLM_ERR_REG_DLM_RFLM_RDFIFO_STATE_SM_ERR mBIT(38)
3941 #define VXGE_HAL_DLM_ERR_REG_DLM_RFLM_STATE_SM_ERR mBIT(39)
3942 #define VXGE_HAL_DLM_ERR_REG_DLM_RIRR_RDMEM_DATA_STATE_SM_ERR mBIT(40)
3943 #define VXGE_HAL_DLM_ERR_REG_DLM_RPTR_ALLOC_STATE_SM_ERR mBIT(41)
3944 #define VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_RDFIFO_STATE_SM_ERR mBIT(42)
3945 #define VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_STATE_SM_ERR mBIT(43)
3946 #define VXGE_HAL_DLM_ERR_REG_DLM_RWRQ_STATE_SM_ERR mBIT(44)
3947 #define VXGE_HAL_DLM_ERR_REG_DLM_RXACK_STATE_SM_ERR mBIT(45)
3948 #define VXGE_HAL_DLM_ERR_REG_DLM_RXLIRR_STATE_SM_ERR mBIT(46)
3949 #define VXGE_HAL_DLM_ERR_REG_DLM_RXRIRR_STATE_SM_ERR mBIT(47)
3950 #define VXGE_HAL_DLM_ERR_REG_DLM_TXACK_RETX_STATE_SM_ERR mBIT(48)
3951 #define VXGE_HAL_DLM_ERR_REG_DLM_TXACK_STATE_SM_ERR mBIT(49)
3952 #define VXGE_HAL_DLM_ERR_REG_DLM_TXLIRR_STATE_SM_ERR mBIT(50)
3953 #define VXGE_HAL_DLM_ERR_REG_DLM_TXRIRR_RETX_STATE_SM_ERR mBIT(51)
3954 #define VXGE_HAL_DLM_ERR_REG_DLM_TXRIRR_STATE_SM_ERR mBIT(52)
3955 #define VXGE_HAL_DLM_ERR_REG_DLM_PREFETCH_ERR mBIT(53)
3956 #define VXGE_HAL_DLM_ERR_REG_DLM_AFLM_FIFO_ERR mBIT(55)
3957 #define VXGE_HAL_DLM_ERR_REG_DLM_RFLM_FIFO_ERR mBIT(56)
3958 #define VXGE_HAL_DLM_ERR_REG_DLM_LFLM_FIFO_ERR mBIT(57)
3959 #define VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_FIFO_ERR mBIT(58)
3960 #define VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_FIFO_ERR mBIT(59)
3961 #define VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_FIFO_ERR mBIT(60)
3962 #define VXGE_HAL_DLM_ERR_REG_DLM_ACK_PTR_FIFO_ERR mBIT(61)
3963 #define VXGE_HAL_DLM_ERR_REG_DLM_RIRR_PTR_FIFO_ERR mBIT(62)
3964 #define VXGE_HAL_DLM_ERR_REG_DLM_LIRR_PTR_FIFO_ERR mBIT(63)
3968 #define VXGE_HAL_OES_ERR_REG_OES_INPUT_ARB_SM_ERR mBIT(0)
3969 #define VXGE_HAL_OES_ERR_REG_OES_PEND_ARB_SM_ERR mBIT(1)
3970 #define VXGE_HAL_OES_ERR_REG_OES_RXSEG_FIFO_ERR mBIT(2)
3971 #define VXGE_HAL_OES_ERR_REG_OES_RXEVT_FIFO_ERR mBIT(3)
3972 #define VXGE_HAL_OES_ERR_REG_OES_TXTDB_FIFO_ERR mBIT(4)
3973 #define VXGE_HAL_OES_ERR_REG_OES_RXTX_FIFO_ERR mBIT(5)
3974 #define VXGE_HAL_OES_ERR_REG_OES_TXIMSG_FIFO_ERR mBIT(6)
3975 #define VXGE_HAL_OES_ERR_REG_OES_TXCONT_FIFO_ERR mBIT(7)
3980 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PA_SG_ERR mBIT(2)
3981 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PB_SG_ERR mBIT(3)
3984 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_TRACE_SG_ERR mBIT(8)
3985 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_IMM_SG_ERR mBIT(9)
3986 #define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PA_SG_ERR mBIT(10)
3987 #define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PB_SG_ERR mBIT(11)
3988 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PA_SG_ERR mBIT(12)
3989 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PB_SG_ERR mBIT(13)
3990 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_STG_SG_ERR mBIT(14)
3992 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PA_DB_ERR mBIT(18)
3993 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PB_DB_ERR mBIT(19)
3996 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_TRACE_DB_ERR mBIT(24)
3997 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_IMM_DB_ERR mBIT(25)
3998 #define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PA_DB_ERR mBIT(26)
3999 #define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PB_DB_ERR mBIT(27)
4000 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PA_DB_ERR mBIT(28)
4001 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PB_DB_ERR mBIT(29)
4002 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_STG_DB_ERR mBIT(30)
4003 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_SM_ERR mBIT(32)
4004 #define VXGE_HAL_TXPE_ERR_REG_TXPE_IMSGIN_SM_ERR mBIT(33)
4005 #define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_SM_ERR mBIT(34)
4006 #define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_TCE_CHOICE_SM_ERR mBIT(35)
4007 #define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_DIV_SM_ERR mBIT(36)
4008 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_SM_ERR mBIT(37)
4009 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_RES_SM_ERR mBIT(38)
4010 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_NACK_SM_ERR mBIT(39)
4011 #define VXGE_HAL_TXPE_ERR_REG_TXPE_RDTCE_SM_ERR mBIT(40)
4012 #define VXGE_HAL_TXPE_ERR_REG_TXPE_CMGIF_RDRQ_SM_ERR mBIT(41)
4013 #define VXGE_HAL_TXPE_ERR_REG_TXPE_CMGIF_READDRES_SM_ERR mBIT(42)
4014 #define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_CTXT_SM_ERR mBIT(43)
4015 #define VXGE_HAL_TXPE_ERR_REG_TXPE_PRI_TCE_UPDATE_SM_ERR mBIT(44)
4016 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_GET_SM_ERR mBIT(45)
4017 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_DONE_SM_ERR mBIT(46)
4018 #define VXGE_HAL_TXPE_ERR_REG_TXPE_INIT_SM_ERR mBIT(47)
4019 #define VXGE_HAL_TXPE_ERR_REG_TXPE_FETCH_SM_ERR mBIT(48)
4020 #define VXGE_HAL_TXPE_ERR_REG_TXPE_HOG_SM_ERR mBIT(49)
4021 #define VXGE_HAL_TXPE_ERR_REG_TXPE_PMON_SM_ERR mBIT(50)
4022 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SM_ERR mBIT(51)
4023 #define VXGE_HAL_TXPE_ERR_REG_TXPE_NCM_CTXT_SM_ERR mBIT(52)
4024 #define VXGE_HAL_TXPE_ERR_REG_TXPE_NCM_MEM_SM_ERR mBIT(53)
4025 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_RQ_SM_ERR mBIT(54)
4026 #define VXGE_HAL_TXPE_ERR_REG_TXPE_RDRES_PHASE_ERR mBIT(55)
4027 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_XLMI_SERR mBIT(56)
4028 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_WRP_ERR mBIT(57)
4029 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_FIFO_ERR mBIT(58)
4030 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_DFIFO_ERR mBIT(59)
4031 #define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_HFIFO_ERR mBIT(60)
4032 #define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_DIVIDE_ERR mBIT(61)
4033 #define VXGE_HAL_TXPE_ERR_REG_TXPE_PDA_NACK_FIFO_ERR mBIT(62)
4034 #define VXGE_HAL_TXPE_ERR_REG_TXPE_MEM_CONFLICT_ERR mBIT(63)
4052 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_SHADOW_ERR mBIT(0)
4053 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_SHADOW_ERR mBIT(1)
4054 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCM_SHADOW_ERR mBIT(2)
4055 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_SHADOW_ERR mBIT(3)
4056 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_SHADOW_ERR mBIT(4)
4057 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_SHADOW_ERR mBIT(5)
4058 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_SHADOW_ERR mBIT(6)
4059 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_RWM_ERR mBIT(7)
4060 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_RRM_ERR mBIT(8)
4061 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_SCC_ERR mBIT(9)
4062 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_CMM_ERR mBIT(10)
4063 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_OIF_ERR mBIT(11)
4064 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_FPG_ERR mBIT(12)
4065 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_WCC_ERR mBIT(13)
4066 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_WMM_ERR mBIT(14)
4067 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_OIF_ERR mBIT(15)
4068 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_QRI_ERR mBIT(16)
4069 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_ERR mBIT(17)
4070 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_UNDEF_EVENT mBIT(18)
4071 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_BS_ERR mBIT(19)
4072 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_IWP_ERR mBIT(20)
4073 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_LRO_ERR mBIT(21)
4074 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_HDR_ERR mBIT(22)
4075 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_MUX_ERR mBIT(23)
4076 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_RLC_ERR mBIT(24)
4077 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_IPM_DLM_ERR mBIT(25)
4078 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_IPM_MSG_ERR mBIT(26)
4079 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_ARB_ERR mBIT(27)
4080 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_HBI_ERR mBIT(28)
4081 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_OPC_ERR mBIT(29)
4082 #define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_FW_ERR mBIT(32)
4088 #define VXGE_HAL_ONE_CFG_ONE_CFG_RDY mBIT(7)
4092 #define VXGE_HAL_SGRP_IWARP_LRO_ALLOC_ENABLE_IWARP mBIT(7)
4097 #define VXGE_HAL_RPE_CFG0_RCC_MODE mBIT(23)
4099 #define VXGE_HAL_RPE_CFG0_BS_ACK_WQE_PF_ENA mBIT(38)
4100 #define VXGE_HAL_RPE_CFG0_IWARP_ISL_PF_ENA mBIT(39)
4101 #define VXGE_HAL_RPE_CFG0_PDM_FRAME_ECC_ENABLE_N mBIT(43)
4102 #define VXGE_HAL_RPE_CFG0_PDM_RCMD_ECC_ENABLE_N mBIT(44)
4103 #define VXGE_HAL_RPE_CFG0_RCQ_ECC_ENABLE_N mBIT(45)
4104 #define VXGE_HAL_RPE_CFG0_RCO_PBLE_ECC_ENABLE_N mBIT(46)
4105 #define VXGE_HAL_RPE_CFG0_RCM_ECC_ENABLE_N mBIT(47)
4106 #define VXGE_HAL_RPE_CFG0_PDM_FRAME_PHASE_ENABLE mBIT(50)
4107 #define VXGE_HAL_RPE_CFG0_DLM_RCMD_PHASE_ENABLE mBIT(51)
4108 #define VXGE_HAL_RPE_CFG0_MSG_RCMD_PHASE_ENABLE mBIT(52)
4109 #define VXGE_HAL_RPE_CFG0_PDM_RCMD_PHASE_ENABLE mBIT(53)
4110 #define VXGE_HAL_RPE_CFG0_RCQ_PHASE_ENABLE mBIT(54)
4111 #define VXGE_HAL_RPE_CFG0_RCO_PBLE_PHASE_ENABLE mBIT(55)
4113 #define VXGE_HAL_RPE_CFG1_WQEOWN_LRO_CTR_ENA mBIT(5)
4114 #define VXGE_HAL_RPE_CFG1_WQEOWN_BS_CTR_ENA mBIT(6)
4115 #define VXGE_HAL_RPE_CFG1_WQEOWN_IWARP_CTR_ENA mBIT(7)
4130 #define VXGE_HAL_RPE_CFG2_RDMA_WRITE_ORDER_ENABLE mBIT(49)
4131 #define VXGE_HAL_RPE_CFG2_RDMA_RDRESP_ORDER_ENABLE mBIT(50)
4132 #define VXGE_HAL_RPE_CFG2_RDMA_SEND_ORDER_ENABLE mBIT(51)
4133 #define VXGE_HAL_RPE_CFG2_RDMA_RDREQ_ORDER_ENABLE mBIT(52)
4134 #define VXGE_HAL_RPE_CFG2_RDMA_TERMINATE_ORDER_ENABLE mBIT(53)
4135 #define VXGE_HAL_RPE_CFG2_IWARP_MISALIGNED_ORDER_ENABLE mBIT(54)
4136 #define VXGE_HAL_RPE_CFG2_IWARP_TIMER_ORDER_ENABLE mBIT(55)
4137 #define VXGE_HAL_RPE_CFG2_IWARP_IMSG_ORDER_ENABLE mBIT(56)
4138 #define VXGE_HAL_RPE_CFG2_BS_IWARP_ACK_ORDER_ENABLE mBIT(57)
4139 #define VXGE_HAL_RPE_CFG2_BS_DATA_ORDER_ENABLE mBIT(58)
4140 #define VXGE_HAL_RPE_CFG2_BS_TIMER_ORDER_ENABLE mBIT(59)
4141 #define VXGE_HAL_RPE_CFG2_BS_IMSG_ORDER_ENABLE mBIT(60)
4142 #define VXGE_HAL_RPE_CFG2_LRO_FRAME_ORDER_ENABLE mBIT(61)
4143 #define VXGE_HAL_RPE_CFG2_LRO_TIMER_ORDER_ENABLE mBIT(62)
4144 #define VXGE_HAL_RPE_CFG2_LRO_IMSG_ORDER_ENABLE mBIT(63)
4148 #define VXGE_HAL_RPE_CFG5_LRO_IGNORE_RPA_PARSE_ERRS mBIT(4)
4149 #define VXGE_HAL_RPE_CFG5_LRO_IGNORE_FRM_INT_ERRS mBIT(5)
4150 #define VXGE_HAL_RPE_CFG5_LRO_IGNORE_L3_CSUM_ERRS mBIT(6)
4151 #define VXGE_HAL_RPE_CFG5_LRO_IGNORE_L4_CSUM_ERRS mBIT(7)
4152 #define VXGE_HAL_RPE_CFG5_LRO_NORM_SCATTER_IPV4_OPTIONS mBIT(14)
4153 #define VXGE_HAL_RPE_CFG5_LRO_NORM_SCATTER_IPV6_EXTHDRS mBIT(15)
4154 #define VXGE_HAL_RPE_CFG5_USE_CONCISE_ADAPTIVE_LRO_CQE mBIT(22)
4155 #define VXGE_HAL_RPE_CFG5_USE_CONCISE_PRECONFIG_LRO_CQE mBIT(23)
4167 #define VXGE_HAL_PE_CTXT_SCC_TRIGGER_READ mBIT(7)
4171 #define VXGE_HAL_PE_CTXT_NP_XFER mBIT(55)
4172 #define VXGE_HAL_PE_CTXT_NP_SPACER mBIT(63)
4174 #define VXGE_HAL_PE_CFG_RXPE_ECC_ENABLE_N mBIT(7)
4175 #define VXGE_HAL_PE_CFG_TXPE_ECC_ENABLE_N mBIT(15)
4176 #define VXGE_HAL_PE_CFG_DLM_ECC_ENABLE_N mBIT(23)
4177 #define VXGE_HAL_PE_CFG_CDP_ECC_ENABLE_N mBIT(31)
4178 #define VXGE_HAL_PE_CFG_PET_ECC_ENABLE_N mBIT(39)
4181 #define VXGE_HAL_PE_STATS_CMD_GO mBIT(7)
4182 #define VXGE_HAL_PE_STATS_CMD_SELECT_TXPE mBIT(15)
4189 #define VXGE_HAL_RXPE_CFG_FW_EXTEND_FP mBIT(7)
4190 #define VXGE_HAL_RXPE_CFG_RETXK_SP_DONE mBIT(15)
4193 #define VXGE_HAL_PE_XT_CTRL1_ENABLE_GO_FOR_WR mBIT(23)
4194 #define VXGE_HAL_PE_XT_CTRL1_IRAM_READ mBIT(27)
4195 #define VXGE_HAL_PE_XT_CTRL1_TXP_IRAM_SEL mBIT(29)
4196 #define VXGE_HAL_PE_XT_CTRL1_RXP0_IRAM_SEL mBIT(30)
4197 #define VXGE_HAL_PE_XT_CTRL1_RXP1_IRAM_SEL mBIT(31)
4198 #define VXGE_HAL_PE_XT_CTRL1_TXP_IRAM_ECC_ENABLE_N mBIT(37)
4199 #define VXGE_HAL_PE_XT_CTRL1_RXP0_IRAM_ECC_ENABLE_N mBIT(38)
4200 #define VXGE_HAL_PE_XT_CTRL1_RXP1_IRAM_ECC_ENABLE_N mBIT(39)
4201 #define VXGE_HAL_PE_XT_CTRL1_TXP_DRAM_ECC_ENABLE_N mBIT(46)
4202 #define VXGE_HAL_PE_XT_CTRL1_RXP_DRAM_ECC_ENABLE_N mBIT(47)
4203 #define VXGE_HAL_PE_XT_CTRL1_TXP_RUNSTALL mBIT(53)
4204 #define VXGE_HAL_PE_XT_CTRL1_RXP0_RUNSTALL mBIT(54)
4205 #define VXGE_HAL_PE_XT_CTRL1_RXP1_RUNSTALL mBIT(55)
4206 #define VXGE_HAL_PE_XT_CTRL1_TXP_BRESET mBIT(61)
4207 #define VXGE_HAL_PE_XT_CTRL1_RXP0_BRESET mBIT(62)
4208 #define VXGE_HAL_PE_XT_CTRL1_RXP1_BRESET mBIT(63)
4212 #define VXGE_HAL_PE_XT_CTRL3_GO mBIT(63)
4229 #define VXGE_HAL_PET_TIMER_BP_CTRL_RD_XON mBIT(7)
4230 #define VXGE_HAL_PET_TIMER_BP_CTRL_WR_XON mBIT(15)
4231 #define VXGE_HAL_PET_TIMER_BP_CTRL_ROCRC_BYP mBIT(23)
4232 #define VXGE_HAL_PET_TIMER_BP_CTRL_H2L_BYP mBIT(31)
4239 #define VXGE_HAL_DLM_CFG_AWRQ_PHASE_ENABLE mBIT(7)
4241 #define VXGE_HAL_DLM_CFG_LWRQ_PHASE_ENABLE mBIT(23)
4252 #define VXGE_HAL_TXPE_PMON_GO mBIT(15)
4268 #define VXGE_HAL_OES_INEVT_CFG_SP_WRR mBIT(63)
4298 #define VXGE_HAL_OES_PENDEVT_CFG_SP_WRR mBIT(63)
4337 #define VXGE_HAL_NOA_WCT_CTRL_VP_INT_NUM mBIT(0)
4346 #define VXGE_HAL_RX_MULTI_CAST_CTRL1_ENABLE mBIT(7)
4350 #define VXGE_HAL_RXDM_DBG_RD_ENABLE mBIT(31)
4358 #define VXGE_HAL_TIM_STATUS_TIM_RESET_IN_PROGRESS mBIT(0)
4360 #define VXGE_HAL_TIM_ECC_ENABLE_VBLS_N mBIT(7)
4361 #define VXGE_HAL_TIM_ECC_ENABLE_BMAP_N mBIT(15)
4362 #define VXGE_HAL_TIM_ECC_ENABLE_BMAP_MSG_N mBIT(23)
4364 #define VXGE_HAL_TIM_BP_CTRL_RD_XON mBIT(7)
4365 #define VXGE_HAL_TIM_BP_CTRL_WR_XON mBIT(15)
4366 #define VXGE_HAL_TIM_BP_CTRL_ROCRC_BYP mBIT(23)
4374 #define VXGE_HAL_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT mBIT(7)
4375 #define VXGE_HAL_GCMG2_INT_STATUS_GCP_ERR_GCP_INT mBIT(15)
4376 #define VXGE_HAL_GCMG2_INT_STATUS_CMC_ERR_CMC_INT mBIT(23)
4381 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR mBIT(8)
4382 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR mBIT(9)
4383 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR mBIT(10)
4384 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR mBIT(11)
4385 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR mBIT(12)
4386 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR mBIT(13)
4387 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR mBIT(14)
4388 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR mBIT(15)
4389 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR mBIT(16)
4390 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR mBIT(17)
4391 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR mBIT(18)
4392 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR mBIT(19)
4393 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR mBIT(20)
4394 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW mBIT(21)
4395 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW mBIT(22)
4396 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR mBIT(23)
4397 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW mBIT(24)
4398 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW mBIT(25)
4399 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR mBIT(26)
4400 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR mBIT(27)
4401 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR mBIT(28)
4402 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR mBIT(29)
4403 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR mBIT(30)
4404 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR mBIT(31)
4405 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR mBIT(32)
4406 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR mBIT(33)
4407 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR mBIT(34)
4408 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR mBIT(35)
4412 #define VXGE_HAL_CMC_ERR_REG_CMC_CMC_SM_ERR mBIT(0)
4416 #define VXGE_HAL_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR mBIT(0)
4417 #define VXGE_HAL_GCP_ERR_REG_CP_STC2CP_FIFO_ERR mBIT(1)
4418 #define VXGE_HAL_GCP_ERR_REG_CP_STE2CP_FIFO_ERR mBIT(2)
4419 #define VXGE_HAL_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR mBIT(3)
4579 #define VXGE_HAL_GXTMC_CFG_CMC_PRI mBIT(7)
4580 #define VXGE_HAL_GXTMC_CFG_GPSYNC_WAIT_TOKEN_ENABLE mBIT(13)
4581 #define VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_TIMER_ENABLE mBIT(14)
4582 #define VXGE_HAL_GXTMC_CFG_GPSYNC_SRC_NOTIFY_ENABLE mBIT(15)
4584 #define VXGE_HAL_GXTMC_CFG_BDT_MEM_ECC_ENABLE_N mBIT(31)
4588 #define VXGE_HAL_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT mBIT(7)
4589 #define VXGE_HAL_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT mBIT(15)
4590 #define VXGE_HAL_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT mBIT(23)
4594 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR mBIT(2)
4595 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR mBIT(3)
4596 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR mBIT(4)
4597 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR mBIT(5)
4598 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR mBIT(6)
4599 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR mBIT(7)
4600 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR mBIT(8)
4601 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR mBIT(9)
4602 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR mBIT(10)
4603 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR mBIT(11)
4604 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR mBIT(12)
4605 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR mBIT(13)
4606 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR mBIT(14)
4607 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR mBIT(15)
4608 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR mBIT(16)
4609 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR mBIT(17)
4610 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR mBIT(18)
4611 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR mBIT(19)
4612 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR mBIT(20)
4613 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR mBIT(21)
4614 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR mBIT(22)
4615 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR mBIT(23)
4616 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR mBIT(24)
4617 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR mBIT(25)
4618 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR mBIT(26)
4619 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR mBIT(27)
4620 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR mBIT(28)
4621 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR mBIT(29)
4622 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR mBIT(30)
4623 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR mBIT(31)
4624 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR mBIT(32)
4625 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR mBIT(33)
4626 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR mBIT(34)
4627 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR mBIT(35)
4628 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR mBIT(36)
4629 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR mBIT(37)
4630 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR mBIT(38)
4631 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR mBIT(39)
4632 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR mBIT(40)
4633 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR mBIT(41)
4634 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR mBIT(42)
4635 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR mBIT(43)
4636 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR mBIT(44)
4637 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR mBIT(45)
4638 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR mBIT(46)
4639 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR mBIT(47)
4640 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR mBIT(48)
4641 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR mBIT(49)
4642 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR mBIT(50)
4643 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR mBIT(51)
4644 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR mBIT(52)
4645 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR mBIT(53)
4647 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR mBIT(56)
4648 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR mBIT(57)
4654 #define VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_SG_ERR mBIT(10)
4655 #define VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_SG_ERR mBIT(11)
4656 #define VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_SG_ERR mBIT(12)
4657 #define VXGE_HAL_CP_ERR_REG_CP_DMA2CP_SG_ERR mBIT(13)
4658 #define VXGE_HAL_CP_ERR_REG_CP_MP2CP_SG_ERR mBIT(14)
4659 #define VXGE_HAL_CP_ERR_REG_CP_QCC2CP_SG_ERR mBIT(15)
4663 #define VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_DB_ERR mBIT(34)
4664 #define VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_DB_ERR mBIT(35)
4665 #define VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_DB_ERR mBIT(36)
4666 #define VXGE_HAL_CP_ERR_REG_CP_DMA2CP_DB_ERR mBIT(37)
4667 #define VXGE_HAL_CP_ERR_REG_CP_MP2CP_DB_ERR mBIT(38)
4668 #define VXGE_HAL_CP_ERR_REG_CP_QCC2CP_DB_ERR mBIT(39)
4670 #define VXGE_HAL_CP_ERR_REG_CP_H2L2CP_FIFO_ERR mBIT(48)
4671 #define VXGE_HAL_CP_ERR_REG_CP_STC2CP_FIFO_ERR mBIT(49)
4672 #define VXGE_HAL_CP_ERR_REG_CP_STE2CP_FIFO_ERR mBIT(50)
4673 #define VXGE_HAL_CP_ERR_REG_CP_TTE2CP_FIFO_ERR mBIT(51)
4674 #define VXGE_HAL_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR mBIT(52)
4675 #define VXGE_HAL_CP_ERR_REG_CP_CP2DMA_FIFO_ERR mBIT(53)
4676 #define VXGE_HAL_CP_ERR_REG_CP_DAM2CP_FIFO_ERR mBIT(54)
4677 #define VXGE_HAL_CP_ERR_REG_CP_MP2CP_FIFO_ERR mBIT(55)
4678 #define VXGE_HAL_CP_ERR_REG_CP_QCC2CP_FIFO_ERR mBIT(56)
4679 #define VXGE_HAL_CP_ERR_REG_CP_DMA2CP_FIFO_ERR mBIT(57)
4680 #define VXGE_HAL_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR mBIT(60)
4681 #define VXGE_HAL_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR mBIT(61)
4682 #define VXGE_HAL_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR mBIT(62)
4683 #define VXGE_HAL_CP_ERR_REG_CP_PIFT_CREDIT_ERR mBIT(63)
4687 #define VXGE_HAL_CP_XT_CTRL1_CP_WAKEUP mBIT(47)
4688 #define VXGE_HAL_CP_XT_CTRL1_CP_RUNSTALL mBIT(55)
4689 #define VXGE_HAL_CP_XT_CTRL1_CP_BRESET mBIT(63)
4691 #define VXGE_HAL_CP_GEN_CFG_MULT_DMA_RD_REQ_ENA mBIT(7)
4692 #define VXGE_HAL_CP_GEN_CFG_DMA_RD_PER_VPLANE_CHK_ENA mBIT(15)
4693 #define VXGE_HAL_CP_GEN_CFG_DMA_RD_XON_CHK_ENA mBIT(23)
4694 #define VXGE_HAL_CP_GEN_CFG_CAUSE_INT_IS_CRITICAL mBIT(31)
4696 #define VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_INFO_INT mBIT(47)
4697 #define VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT mBIT(55)
4698 #define VXGE_HAL_CP_EXC_REG_CP_CP_SERR mBIT(63)
4707 #define VXGE_HAL_XTMC_IMG_CTRL0_ENABLE_GO mBIT(15)
4708 #define VXGE_HAL_XTMC_IMG_CTRL0_IMG_LD_COMPLETE mBIT(23)
4709 #define VXGE_HAL_XTMC_IMG_CTRL0_LAST_DATA mBIT(31)
4714 #define VXGE_HAL_XTMC_IMG_CTRL2_XTMC_LD_BANK_AVAIL mBIT(63)
4716 #define VXGE_HAL_XTMC_IMG_CTRL3_XTMC_ALL_DATA_WRITTEN mBIT(63)
4718 #define VXGE_HAL_XTMC_IMG_CTRL4_GO mBIT(63)
4720 #define VXGE_HAL_PXTMC_CFG0_XT_PIF_SRAM_ECC_ENABLE_N mBIT(3)
4721 #define VXGE_HAL_PXTMC_CFG0_XT_PIF_SRAM_PHASE_ENA mBIT(7)
4722 #define VXGE_HAL_PXTMC_CFG0_MXP_RD_PROT_ENA mBIT(11)
4723 #define VXGE_HAL_PXTMC_CFG0_MXP_WR_PROT_ENA mBIT(15)
4724 #define VXGE_HAL_PXTMC_CFG0_UXP_RD_PROT_ENA mBIT(19)
4725 #define VXGE_HAL_PXTMC_CFG0_UXP_WR_PROT_ENA mBIT(23)
4726 #define VXGE_HAL_PXTMC_CFG0_CXP_RD_PROT_ENA mBIT(27)
4727 #define VXGE_HAL_PXTMC_CFG0_CXP_WR_PROT_ENA mBIT(31)
4728 #define VXGE_HAL_PXTMC_CFG0_INVALID_ADDR_CHECK_ENA mBIT(39)
4729 #define VXGE_HAL_PXTMC_CFG0_SUPPRESS_RD_ON_ADDR_ERR mBIT(43)
4730 #define VXGE_HAL_PXTMC_CFG0_SUPPRESS_WR_ON_ADDR_ERR mBIT(47)
4731 #define VXGE_HAL_PXTMC_CFG0_ARB_DURING_4BYTE_WR_ENA mBIT(55)
4736 #define VXGE_HAL_PXTMC_CFG1_PGSYNC_WAIT_TOKEN_ENABLE mBIT(29)
4737 #define VXGE_HAL_PXTMC_CFG1_PGSYNC_CNTDOWN_TIMER_ENABLE mBIT(30)
4738 #define VXGE_HAL_PXTMC_CFG1_PGSYNC_SRC_NOTIFY_ENABLE mBIT(31)
4781 #define VXGE_HAL_MSG_INT_STATUS_TIM_ERR_TIM_INT mBIT(7)
4782 #define VXGE_HAL_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT mBIT(60)
4783 #define VXGE_HAL_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT mBIT(61)
4784 #define VXGE_HAL_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT mBIT(62)
4785 #define VXGE_HAL_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT mBIT(63)
4788 #define VXGE_HAL_TIM_ERR_REG_TIM_VBLS_SG_ERR mBIT(4)
4789 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR mBIT(5)
4790 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR mBIT(6)
4791 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR mBIT(7)
4792 #define VXGE_HAL_TIM_ERR_REG_TIM_VBLS_DB_ERR mBIT(12)
4793 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR mBIT(13)
4794 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR mBIT(14)
4795 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR mBIT(15)
4796 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR mBIT(18)
4797 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR mBIT(19)
4798 #define VXGE_HAL_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR mBIT(20)
4799 #define VXGE_HAL_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR mBIT(22)
4800 #define VXGE_HAL_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR mBIT(23)
4801 #define VXGE_HAL_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH mBIT(46)
4802 #define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n) mBIT(n)
4806 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR mBIT(0)
4807 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR mBIT(1)
4808 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR mBIT(2)
4809 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR mBIT(3)
4810 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR mBIT(4)
4811 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR mBIT(5)
4812 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR mBIT(6)
4813 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR mBIT(7)
4814 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR mBIT(8)
4815 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR mBIT(10)
4816 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR mBIT(12)
4817 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR mBIT(14)
4818 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR mBIT(16)
4819 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR mBIT(17)
4820 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR mBIT(18)
4821 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR mBIT(19)
4822 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR mBIT(20)
4823 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR mBIT(21)
4824 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR mBIT(26)
4825 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR mBIT(27)
4826 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR mBIT(29)
4827 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR mBIT(31)
4828 #define VXGE_HAL_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR mBIT(33)
4829 #define VXGE_HAL_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR mBIT(34)
4830 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR mBIT(35)
4831 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR mBIT(36)
4832 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR mBIT(38)
4833 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR mBIT(39)
4834 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR mBIT(41)
4835 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR mBIT(43)
4836 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR mBIT(45)
4837 #define VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR mBIT(47)
4838 #define VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR mBIT(48)
4839 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR mBIT(49)
4840 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR mBIT(50)
4841 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR mBIT(51)
4842 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR mBIT(52)
4843 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR mBIT(53)
4844 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR mBIT(54)
4845 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR mBIT(55)
4846 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR mBIT(56)
4847 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR mBIT(57)
4848 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR mBIT(58)
4849 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR mBIT(59)
4850 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR mBIT(60)
4851 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR mBIT(61)
4852 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR mBIT(62)
4853 #define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR mBIT(63)
4857 #define VXGE_HAL_MSG_XT_CTRL_MXP_CAUSE_INT_IS_CRITICAL mBIT(35)
4858 #define VXGE_HAL_MSG_XT_CTRL_UXP_CAUSE_INT_IS_CRITICAL mBIT(39)
4859 #define VXGE_HAL_MSG_XT_CTRL_MXP_WAKEUP mBIT(46)
4860 #define VXGE_HAL_MSG_XT_CTRL_UXP_WAKEUP mBIT(47)
4861 #define VXGE_HAL_MSG_XT_CTRL_MXP_RUNSTALL mBIT(54)
4862 #define VXGE_HAL_MSG_XT_CTRL_UXP_RUNSTALL mBIT(55)
4863 #define VXGE_HAL_MSG_XT_CTRL_MXP_BRESET mBIT(62)
4864 #define VXGE_HAL_MSG_XT_CTRL_UXP_BRESET mBIT(63)
4868 #define VXGE_HAL_MSG_DISPATCH_MESS_TYPE_ENABLE mBIT(55)
4873 #define VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT mBIT(50)
4874 #define VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT mBIT(51)
4875 #define VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT mBIT(54)
4876 #define VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT mBIT(55)
4877 #define VXGE_HAL_MSG_EXC_REG_MP_MXP_SERR mBIT(62)
4878 #define VXGE_HAL_MSG_EXC_REG_UP_UXP_SERR mBIT(63)
4887 #define VXGE_HAL_MSG_DIRECT_PIC_PIPELINE_EN mBIT(55)
4888 #define VXGE_HAL_MSG_DIRECT_PIC_UMQ_WRITE_ENABLE mBIT(56)
4895 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR mBIT(0)
4896 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR mBIT(1)
4897 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR mBIT(2)
4898 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR mBIT(3)
4899 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR mBIT(4)
4900 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR mBIT(5)
4901 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR mBIT(6)
4902 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR mBIT(7)
4903 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR mBIT(8)
4904 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR mBIT(9)
4905 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR mBIT(10)
4906 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR mBIT(11)
4908 mBIT(12)
4910 mBIT(13)
4912 mBIT(14)
4914 mBIT(15)
4916 mBIT(16)
4918 mBIT(17)
4920 mBIT(18)
4921 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR mBIT(19)
4922 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR mBIT(20)
4923 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR mBIT(21)
4924 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR mBIT(22)
4925 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR mBIT(23)
4926 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR mBIT(24)
4927 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR mBIT(25)
4928 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR mBIT(26)
4929 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR mBIT(27)
4930 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR mBIT(28)
4931 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR mBIT(29)
4933 mBIT(30)
4935 mBIT(31)
4937 mBIT(32)
4938 #define VXGE_HAL_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR mBIT(33)
4939 #define VXGE_HAL_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR mBIT(34)
4940 #define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR mBIT(62)
4941 #define VXGE_HAL_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR mBIT(63)
4945 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0 mBIT(0)
4946 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1 mBIT(1)
4947 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2 mBIT(2)
4948 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3 mBIT(3)
4949 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4 mBIT(4)
4950 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5 mBIT(5)
4951 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6 mBIT(6)
4952 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7 mBIT(7)
4953 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0 mBIT(8)
4954 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1 mBIT(9)
4955 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0 mBIT(16)
4956 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1 mBIT(17)
4957 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2 mBIT(18)
4958 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3 mBIT(19)
4959 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4 mBIT(20)
4960 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5 mBIT(21)
4961 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6 mBIT(22)
4962 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7 mBIT(23)
4963 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0 mBIT(24)
4964 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1 mBIT(25)
4965 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 mBIT(32)
4966 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 mBIT(33)
4967 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 mBIT(34)
4968 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 mBIT(35)
4969 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 mBIT(36)
4970 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 mBIT(37)
4971 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 mBIT(38)
4972 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 mBIT(39)
4973 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 mBIT(40)
4974 #define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 mBIT(41)
4975 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 mBIT(48)
4976 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 mBIT(49)
4977 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 mBIT(50)
4978 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 mBIT(51)
4979 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 mBIT(52)
4980 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 mBIT(53)
4981 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 mBIT(54)
4982 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 mBIT(55)
4983 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 mBIT(56)
4984 #define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1 mBIT(57)
4988 #define VXGE_HAL_UMQ_IR_TEST_BYTE_NOTIFY_PULSE mBIT(3)
4990 #define VXGE_HAL_MSG_BP_CTRL_RD_XON_EN mBIT(7)
4991 #define VXGE_HAL_MSG_BP_CTRL_WR_XON_E mBIT(15)
4992 #define VXGE_HAL_MSG_BP_CTRL_ROCRC_BYP_EN mBIT(23)
4996 #define VXGE_HAL_UMQ_BWR_PFCH_INIT_NOTIFY_PULSE mBIT(3)
5000 #define VXGE_HAL_UMQ_BWR_EOL_LATENCY_NOTIFY_PULSE mBIT(3)
5004 #define VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP mBIT(3)
5005 #define VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP mBIT(7)
5006 #define VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP mBIT(11)
5007 #define VXGE_HAL_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIF mBIT(15)
5011 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR mBIT(0)
5012 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR mBIT(1)
5017 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR mBIT(6)
5018 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR mBIT(7)
5023 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR mBIT(12)
5024 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR mBIT(13)
5031 #define VXGE_HAL_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR mBIT(31)
5044 #define VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM mBIT(3)
5045 #define VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF mBIT(7)
5046 #define VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM mBIT(11)
5052 #define VXGE_HAL_FAU_AUTO_LRO_CONTROL_OPERATION_TYPE mBIT(7)
5057 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_HAS_VLAN mBIT(14)
5058 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_IS_IPV6 mBIT(15)
5074 #define VXGE_HAL_FAU_LAG_CFG_INCR_RX_AGGR_STATS mBIT(7)
5078 #define VXGE_HAL_FAU_MPA_CFG_CRC_CHK_EN mBIT(3)
5079 #define VXGE_HAL_FAU_MPA_CFG_MRK_LEN_CHK_EN mBIT(7)
5090 #define VXGE_HAL_TPA_INT_STATUS_ORP_ERR_ORP_INT mBIT(15)
5091 #define VXGE_HAL_TPA_INT_STATUS_PTM_ALARM_PTM_INT mBIT(23)
5092 #define VXGE_HAL_TPA_INT_STATUS_TPA_ERROR_TPA_INT mBIT(31)
5095 #define VXGE_HAL_ORP_ERR_REG_ORP_FIFO_SG_ERR mBIT(3)
5096 #define VXGE_HAL_ORP_ERR_REG_ORP_FIFO_DB_ERR mBIT(7)
5097 #define VXGE_HAL_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR mBIT(11)
5098 #define VXGE_HAL_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR mBIT(15)
5099 #define VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR mBIT(19)
5100 #define VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR mBIT(23)
5101 #define VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR mBIT(27)
5102 #define VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR mBIT(31)
5103 #define VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR mBIT(35)
5104 #define VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR mBIT(39)
5105 #define VXGE_HAL_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR mBIT(43)
5106 #define VXGE_HAL_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR mBIT(47)
5110 #define VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR mBIT(3)
5111 #define VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR mBIT(7)
5112 #define VXGE_HAL_PTM_ALARM_REG_XFMD_RD_FIFO_ERR mBIT(11)
5113 #define VXGE_HAL_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR mBIT(15)
5119 #define VXGE_HAL_TPA_ERROR_REG_TPA_FSM_ERR_ALARM mBIT(3)
5120 #define VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR mBIT(7)
5121 #define VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR mBIT(11)
5125 #define VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N mBIT(7)
5126 #define VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N mBIT(35)
5134 #define VXGE_HAL_ORP_CFG_ORP_FIFO_ECC_ENABLE_N mBIT(15)
5135 #define VXGE_HAL_ORP_CFG_FIFO_PHASE_EN mBIT(23)
5137 #define VXGE_HAL_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N mBIT(3)
5139 #define VXGE_HAL_PTM_PHASE_CFG_FRMM_WR_PHASE_EN mBIT(3)
5140 #define VXGE_HAL_PTM_PHASE_CFG_FRMM_RD_PHASE_EN mBIT(7)
5152 #define VXGE_HAL_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT mBIT(3)
5153 #define VXGE_HAL_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT mBIT(7)
5156 #define VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP mBIT(3)
5157 #define VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT mBIT(7)
5161 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR mBIT(3)
5162 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR mBIT(7)
5163 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR mBIT(11)
5164 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR mBIT(15)
5165 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR mBIT(19)
5166 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR mBIT(23)
5167 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR mBIT(27)
5168 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR mBIT(31)
5169 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR mBIT(35)
5170 #define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR mBIT(39)
5176 #define VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE mBIT(7)
5177 #define VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH mBIT(11)
5178 #define VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE mBIT(15)
5179 #define VXGE_HAL_TXMAC_GEN_CFG1_SCALE_TMAC_UTIL mBIT(27)
5180 #define VXGE_HAL_TXMAC_GEN_CFG1_DISCARD_WHEN_TMAC_DISABLED mBIT(35)
5181 #define VXGE_HAL_TXMAC_GEN_CFG1_IFS_EN mBIT(39)
5189 #define VXGE_HAL_TXMAC_FRMGEN_CFG_EN mBIT(3)
5192 #define VXGE_HAL_TXMAC_FRMGEN_CFG_SEND_TO_WIRE mBIT(15)
5200 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LEN_SEL mBIT(11)
5218 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR mBIT(23)
5220 #define VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN mBIT(3)
5221 #define VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD mBIT(7)
5226 #define VXGE_HAL_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT mBIT(3)
5230 #define VXGE_HAL_LAG_DISTRIB_DEST_MAP_VPATH(n) mBIT(n)
5232 #define VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN mBIT(3)
5233 #define VXGE_HAL_LAG_MARKER_CFG_RESP_EN mBIT(7)
5237 #define VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP mBIT(51)
5239 #define VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS mBIT(3)
5241 #define VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL mBIT(11)
5253 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXC_CHAR1 mBIT(7)
5256 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXC_CHAR2 mBIT(23)
5258 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_BEHAV_CHAR2_NEAR_CHAR1 mBIT(39)
5262 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE0 mBIT(7)
5264 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE1 mBIT(23)
5266 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE2 mBIT(39)
5268 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE3 mBIT(55)
5271 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE0 mBIT(7)
5273 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE1 mBIT(23)
5275 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE2 mBIT(39)
5277 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE3 mBIT(55)
5280 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_BEHAV_COLUMN2_NEAR_COL1 mBIT(7)
5290 #define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_SHC mBIT(31)
5291 #define VXGE_HAL_SHAREDIO_STATUS_PCI_SHARED_IO_MODE mBIT(34)
5298 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_PD_INFINITE mBIT(51)
5299 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_NPD_INFINITE mBIT(55)
5300 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_CPLD_INFINITE mBIT(59)
5305 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_PH_INFINITE mBIT(31)
5306 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_NPH_INFINITE mBIT(35)
5307 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_CPLH_INFINITE mBIT(39)
5331 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_PD_INFINITE mBIT(51)
5332 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_NPD_INFINITE mBIT(55)
5333 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_CPLD_INFINITE mBIT(59)
5338 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_PH_INFINITE mBIT(31)
5339 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_NPH_INFINITE mBIT(35)
5340 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_CPLH_INFINITE mBIT(39)
5363 #define VXGE_HAL_PCIE_LANE_CFG2_STROBE mBIT(0)
5374 #define VXGE_HAL_GENERAL_CFG_ENABLE_FLR_ON_MRIOV_DIS mBIT(0)
5375 #define VXGE_HAL_GENERAL_CFG_ENABLE_FLR_ON_SRIOV_DIS mBIT(1)
5376 #define VXGE_HAL_GENERAL_CFG_MULTI_FUNC_8_MODE mBIT(2)
5377 #define VXGE_HAL_GENERAL_CFG_EN_RST_CPLTO_IN_LUT mBIT(3)
5379 #define VXGE_HAL_GENERAL_CFG_SHARED_IO_MODE mBIT(11)
5383 #define VXGE_HAL_GENERAL_CFG_SNOOP_CPLH_CRDT_ON_BUS mBIT(35)
5385 #define VXGE_HAL_GENERAL_CFG_RX_MEM_ECC_ENABLE_N mBIT(43)
5386 #define VXGE_HAL_GENERAL_CFG_TX_MEM_ECC_ENABLE_N mBIT(47)
5387 #define VXGE_HAL_GENERAL_CFG_MRIOV_CFG_EN mBIT(51)
5388 #define VXGE_HAL_GENERAL_CFG_HIDE_VPD_CAPABILITY mBIT(53)
5389 #define VXGE_HAL_GENERAL_CFG_FORCE_RDS_TO_USE_PF_REQID mBIT(54)
5390 #define VXGE_HAL_GENERAL_CFG_POISON_ADVISORY mBIT(55)
5391 #define VXGE_HAL_GENERAL_CFG_CPL_TIMEOUT_ADVISORY mBIT(56)
5392 #define VXGE_HAL_GENERAL_CFG_UNEXP_CPL_ADVISORY mBIT(57)
5393 #define VXGE_HAL_GENERAL_CFG_UR_ADVISORY mBIT(58)
5394 #define VXGE_HAL_GENERAL_CFG_CA_ADVISORY mBIT(59)
5395 #define VXGE_HAL_GENERAL_CFG_WAIT_FOR_CPLH_CRDT_ON_BUS mBIT(60)
5396 #define VXGE_HAL_GENERAL_CFG_EN_SEND_ERR_MSG_FOR_SERR mBIT(61)
5397 #define VXGE_HAL_GENERAL_CFG_SEND_NF_MSG_FOR_SERR mBIT(62)
5398 #define VXGE_HAL_GENERAL_CFG_VF_MUST_USE_CFG_TYPE0 mBIT(63)
5400 #define VXGE_HAL_START_BIST_START_BIST mBIT(0)
5402 #define VXGE_HAL_BIST_CFG_IGNORE_MEM_RDY mBIT(3)
5403 #define VXGE_HAL_BIST_CFG_ENABLE mBIT(7)
5406 #define VXGE_HAL_PCI_LINK_CONTROL_APP_REQ_RETRY_EN mBIT(3)
5407 #define VXGE_HAL_PCI_LINK_CONTROL_APP_LTSSM_EN mBIT(7)
5427 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_PD_INFINITE mBIT(51)
5428 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_NPD_INFINITE mBIT(55)
5429 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_CPLD_INFINITE mBIT(59)
5437 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_PH_INFINITE mBIT(31)
5438 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_NPH_INFINITE mBIT(35)
5439 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_CPLH_INFINITE mBIT(39)
5444 #define VXGE_HAL_ARBITER_CFG_CHK_PRIORITY_MATCH_ONLY mBIT(15)
5496 #define VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_TRIG_TRIG mBIT(0)
5520 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PIC_INT mBIT(0)
5521 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCI_INT mBIT(1)
5522 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT mBIT(2)
5523 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT mBIT(3)
5524 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT mBIT(4)
5525 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT mBIT(5)
5526 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT mBIT(6)
5527 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT mBIT(7)
5528 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT mBIT(8)
5529 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT mBIT(9)
5530 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT mBIT(10)
5531 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT mBIT(11)
5532 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT mBIT(12)
5533 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_XMAC_INT mBIT(13)
5534 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT mBIT(14)
5535 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TMAC_INT mBIT(15)
5536 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT mBIT(16)
5537 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_FBMC_INT mBIT(17)
5538 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT mBIT(18)
5539 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TPA_INT mBIT(19)
5540 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT mBIT(20)
5541 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_ONE_INT mBIT(21)
5542 #define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_MSG_INT mBIT(22)
5544 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PIC_INT mBIT(0)
5545 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCI_INT mBIT(1)
5546 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_RTDMA_INT mBIT(2)
5547 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_WRDMA_INT mBIT(3)
5548 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT mBIT(4)
5549 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG1_INT mBIT(5)
5550 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG2_INT mBIT(6)
5551 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG3_INT mBIT(7)
5552 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT mBIT(8)
5553 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT mBIT(9)
5554 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG1_INT mBIT(10)
5555 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG2_INT mBIT(11)
5556 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG3_INT mBIT(12)
5557 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_XMAC_INT mBIT(13)
5558 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_RXMAC_INT mBIT(14)
5559 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_TMAC_INT mBIT(15)
5560 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT mBIT(16)
5561 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_FBMC_INT mBIT(17)
5562 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT mBIT(18)
5563 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_TPA_INT mBIT(19)
5564 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_DRBELL_INT mBIT(20)
5565 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_ONE_INT mBIT(21)
5566 #define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_MSG_INT mBIT(22)
5568 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT mBIT(3)
5569 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT mBIT(7)
5570 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT mBIT(11)
5571 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT mBIT(15)
5572 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT mBIT(19)
5574 mBIT(23)
5575 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT mBIT(27)
5577 mBIT(31)
5579 mBIT(32)
5581 mBIT(33)
5583 mBIT(34)
5585 mBIT(35)
5587 mBIT(36)
5589 mBIT(37)
5591 mBIT(38)
5593 mBIT(39)
5595 mBIT(40)
5598 mBIT(41)
5601 mBIT(42)
5604 mBIT(43)
5607 mBIT(44)
5610 mBIT(45)
5613 mBIT(46)
5616 mBIT(47)
5617 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_SRPCIM_TO_MRPCIM_ALARM_INT mBIT(51)
5618 #define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_INT mBIT(55)
5623 #define VXGE_HAL_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG mBIT(3)
5624 #define VXGE_HAL_INI_ERRORS_REG_SCPL_CPL_TIMEOUT mBIT(7)
5625 #define VXGE_HAL_INI_ERRORS_REG_DCPL_FSM_ERR mBIT(11)
5626 #define VXGE_HAL_INI_ERRORS_REG_DCPL_POISON mBIT(12)
5627 #define VXGE_HAL_INI_ERRORS_REG_DCPL_UNSUPPORTED mBIT(15)
5628 #define VXGE_HAL_INI_ERRORS_REG_DCPL_ABORT mBIT(19)
5629 #define VXGE_HAL_INI_ERRORS_REG_INI_TLP_ABORT mBIT(23)
5630 #define VXGE_HAL_INI_ERRORS_REG_INI_DLLP_ABORT mBIT(27)
5631 #define VXGE_HAL_INI_ERRORS_REG_INI_ECRC_ERR mBIT(31)
5632 #define VXGE_HAL_INI_ERRORS_REG_INI_BUF_DB_ERR mBIT(35)
5633 #define VXGE_HAL_INI_ERRORS_REG_INI_BUF_SG_ERR mBIT(39)
5634 #define VXGE_HAL_INI_ERRORS_REG_INI_DATA_OVERFLOW mBIT(43)
5635 #define VXGE_HAL_INI_ERRORS_REG_INI_HDR_OVERFLOW mBIT(47)
5636 #define VXGE_HAL_INI_ERRORS_REG_INI_MRD_SYS_DROP mBIT(51)
5637 #define VXGE_HAL_INI_ERRORS_REG_INI_MWR_SYS_DROP mBIT(55)
5638 #define VXGE_HAL_INI_ERRORS_REG_INI_MRD_CLIENT_DROP mBIT(59)
5639 #define VXGE_HAL_INI_ERRORS_REG_INI_MWR_CLIENT_DROP mBIT(63)
5643 #define VXGE_HAL_DMA_ERRORS_REG_RDARB_FSM_ERR mBIT(3)
5644 #define VXGE_HAL_DMA_ERRORS_REG_WRARB_FSM_ERR mBIT(7)
5645 #define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW mBIT(8)
5646 #define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW mBIT(9)
5647 #define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW mBIT(10)
5648 #define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW mBIT(11)
5649 #define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW mBIT(12)
5650 #define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW mBIT(13)
5651 #define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW mBIT(14)
5652 #define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW mBIT(15)
5653 #define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW mBIT(16)
5654 #define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW mBIT(17)
5655 #define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW mBIT(18)
5656 #define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW mBIT(19)
5657 #define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW mBIT(20)
5658 #define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW mBIT(21)
5659 #define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW mBIT(22)
5660 #define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW mBIT(23)
5661 #define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW mBIT(24)
5662 #define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW mBIT(25)
5663 #define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW mBIT(28)
5664 #define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW mBIT(29)
5665 #define VXGE_HAL_DMA_ERRORS_REG_DBLGEN_FSM_ERR mBIT(32)
5666 #define VXGE_HAL_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR mBIT(33)
5667 #define VXGE_HAL_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR mBIT(34)
5671 #define VXGE_HAL_TGT_ERRORS_REG_TGT_VENDOR_MSG mBIT(0)
5672 #define VXGE_HAL_TGT_ERRORS_REG_TGT_MSG_UNLOCK mBIT(1)
5673 #define VXGE_HAL_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE mBIT(2)
5674 #define VXGE_HAL_TGT_ERRORS_REG_TGT_BOOT_WRITE mBIT(3)
5675 #define VXGE_HAL_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE mBIT(4)
5676 #define VXGE_HAL_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE mBIT(5)
5677 #define VXGE_HAL_TGT_ERRORS_REG_TGT_KDFC_READ mBIT(6)
5678 #define VXGE_HAL_TGT_ERRORS_REG_TGT_USDC_READ mBIT(7)
5679 #define VXGE_HAL_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE mBIT(8)
5680 #define VXGE_HAL_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE mBIT(9)
5681 #define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON mBIT(10)
5682 #define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON mBIT(11)
5683 #define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON mBIT(12)
5684 #define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON mBIT(13)
5685 #define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON mBIT(14)
5686 #define VXGE_HAL_TGT_ERRORS_REG_TGT_NOT_MEM_TLP mBIT(15)
5687 #define VXGE_HAL_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP mBIT(16)
5688 #define VXGE_HAL_TGT_ERRORS_REG_TGT_REQ_FSM_ERR mBIT(17)
5689 #define VXGE_HAL_TGT_ERRORS_REG_TGT_CPL_FSM_ERR mBIT(18)
5690 #define VXGE_HAL_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR mBIT(19)
5691 #define VXGE_HAL_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR mBIT(20)
5692 #define VXGE_HAL_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR mBIT(21)
5696 #define VXGE_HAL_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND mBIT(3)
5697 #define VXGE_HAL_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND mBIT(7)
5698 #define VXGE_HAL_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT mBIT(11)
5699 #define VXGE_HAL_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE mBIT(15)
5700 #define VXGE_HAL_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR mBIT(19)
5701 #define VXGE_HAL_CONFIG_ERRORS_REG_I2C_REQ_COLLISION mBIT(23)
5702 #define VXGE_HAL_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR mBIT(27)
5703 #define VXGE_HAL_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT mBIT(31)
5704 #define VXGE_HAL_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT mBIT(35)
5705 #define VXGE_HAL_CONFIG_ERRORS_REG_CFGM_FSM_ERR mBIT(39)
5706 #define VXGE_HAL_CONFIG_ERRORS_REG_RIC_FSM_ERR mBIT(43)
5707 #define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS mBIT(47)
5708 #define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TIMEOUT mBIT(51)
5709 #define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_FSM_ERR mBIT(55)
5710 #define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR mBIT(59)
5711 #define VXGE_HAL_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT mBIT(63)
5717 #define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR mBIT(11)
5718 #define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL mBIT(15)
5719 #define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL mBIT(19)
5720 #define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL mBIT(23)
5721 #define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR mBIT(35)
5722 #define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL mBIT(39)
5723 #define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL mBIT(43)
5724 #define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL mBIT(47)
5730 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR mBIT(3)
5731 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR mBIT(7)
5732 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR mBIT(11)
5733 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR mBIT(15)
5734 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR mBIT(19)
5735 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR mBIT(23)
5736 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR mBIT(27)
5737 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR mBIT(31)
5738 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET mBIT(35)
5739 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR mBIT(39)
5740 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW mBIT(43)
5742 mBIT(47)
5743 #define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR mBIT(51)
5749 #define VXGE_HAL_PLL_ERRORS_REG_CORE_CMG_PLL_OOL mBIT(3)
5750 #define VXGE_HAL_PLL_ERRORS_REG_CORE_FB_PLL_OOL mBIT(7)
5751 #define VXGE_HAL_PLL_ERRORS_REG_CORE_X_PLL_OOL mBIT(11)
5765 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR mBIT(3)
5766 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR mBIT(7)
5767 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR mBIT(11)
5768 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR mBIT(15)
5769 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR mBIT(19)
5770 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR mBIT(23)
5771 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR mBIT(27)
5772 #define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR mBIT(31)
5778 #define VXGE_HAL_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG mBIT(7)
5780 #define VXGE_HAL_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED mBIT(7)
5789 #define VXGE_HAL_MRPCIM_GENERAL_STATUS1_XGMAC_MISC_INT_ALARM mBIT(11)
5799 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_RD_WRN mBIT(39)
5812 mBIT(40)
5814 mBIT(41)
5816 mBIT(42)
5818 mBIT(43)
5820 mBIT(44)
5822 mBIT(45)
5824 mBIT(46)
5826 mBIT(47)
5828 mBIT(48)
5830 mBIT(49)
5832 mBIT(50)
5834 mBIT(51)
5836 mBIT(52)
5838 mBIT(53)
5840 mBIT(54)
5842 mBIT(55)
5844 mBIT(56)
5845 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_TAGS_DEPLETED mBIT(60)
5846 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_RDA_TAGS mBIT(61)
5847 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_PDA_TAGS mBIT(62)
5849 mBIT(63)
5853 #define VXGE_HAL_TEST_STATUS_PERR_INS_TX_WR_EP_DONE mBIT(3)
5854 #define VXGE_HAL_TEST_STATUS_PERR_INS_TX_RD_EP_DONE mBIT(7)
5855 #define VXGE_HAL_TEST_STATUS_PERR_INS_TX_CPL_EP_DONE mBIT(11)
5856 #define VXGE_HAL_TEST_STATUS_PERR_INS_TX_ECRCERR_DONE mBIT(15)
5857 #define VXGE_HAL_TEST_STATUS_PERR_INS_TX_LCRCERR_DONE mBIT(19)
5858 #define VXGE_HAL_TEST_STATUS_PERR_INS_RX_ECRCERR_DONE mBIT(23)
5859 #define VXGE_HAL_TEST_STATUS_PERR_INS_RX_LCRCERR_DONE mBIT(27)
5869 #define VXGE_HAL_MSIX_TABLE_MASK mBIT(63)
5872 #define VXGE_HAL_MSIX_CTL_WRITE_OR_READ mBIT(15)
5874 #define VXGE_HAL_MSIX_ACCESS_TABLE_MSIX_ACCESS_TABLE mBIT(0)
5878 #define VXGE_HAL_WRITE_ARB_PENDING_WRARB_WRDMA mBIT(3)
5879 #define VXGE_HAL_WRITE_ARB_PENDING_WRARB_RTDMA mBIT(7)
5880 #define VXGE_HAL_WRITE_ARB_PENDING_WRARB_MSG mBIT(11)
5881 #define VXGE_HAL_WRITE_ARB_PENDING_WRARB_STATSB mBIT(15)
5882 #define VXGE_HAL_WRITE_ARB_PENDING_WRARB_INTCTL mBIT(19)
5884 #define VXGE_HAL_READ_ARB_PENDING_RDARB_WRDMA mBIT(3)
5885 #define VXGE_HAL_READ_ARB_PENDING_RDARB_RTDMA mBIT(7)
5886 #define VXGE_HAL_READ_ARB_PENDING_RDARB_DBLGEN mBIT(11)
5888 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR mBIT(0)
5889 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD mBIT(1)
5890 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR mBIT(2)
5891 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD mBIT(3)
5892 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR mBIT(4)
5893 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR mBIT(5)
5904 #define VXGE_HAL_MRPCIM_GENERAL_CFG1_CLEAR_SERR mBIT(7)
5906 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD mBIT(3)
5907 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD mBIT(7)
5908 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD mBIT(11)
5909 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR mBIT(15)
5910 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD mBIT(19)
5911 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX mBIT(23)
5912 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB mBIT(27)
5913 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR mBIT(31)
5914 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE mBIT(43)
5917 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR mBIT(55)
5918 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA mBIT(59)
5919 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS mBIT(63)
5921 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN mBIT(0)
5922 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN mBIT(3)
5923 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN mBIT(7)
5924 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN mBIT(11)
5925 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN mBIT(15)
5926 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN mBIT(19)
5929 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN mBIT(55)
5931 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N mBIT(59)
5932 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN mBIT(63)
5939 #define VXGE_HAL_DIS_FW_PIPELINE_WR_DIS_FW_PIPELINE_WR mBIT(0)
5944 #define VXGE_HAL_PIC_ARBITER_CFG_DMA_READ_EN mBIT(3)
5945 #define VXGE_HAL_PIC_ARBITER_CFG_DMA_WRITE_EN mBIT(7)
5946 #define VXGE_HAL_PIC_ARBITER_CFG_DBLGEN_WRR_EN mBIT(11)
5947 #define VXGE_HAL_PIC_ARBITER_CFG_WRCRDTARB_EN mBIT(15)
5948 #define VXGE_HAL_PIC_ARBITER_CFG_RDCRDTARB_EN mBIT(19)
5959 #define VXGE_HAL_READ_ARBITER_CHECK_PRIORITY_MATCH_ONLY mBIT(39)
5975 #define VXGE_HAL_WRITE_ARBITER_CHECK_PRIORITY_MATCH_ONLY mBIT(55)
5977 #define VXGE_HAL_ADAPTER_CONTROL_ADAPTER_EN mBIT(7)
5978 #define VXGE_HAL_ADAPTER_CONTROL_DISABLE_RIC mBIT(49)
5979 #define VXGE_HAL_ADAPTER_CONTROL_ECC_ENABLE_N mBIT(55)
5982 #define VXGE_HAL_PROGRAM_CFG0_CFGM_TIMEOUT_EN mBIT(11)
5983 #define VXGE_HAL_PROGRAM_CFG0_PIFM_TIMEOUT_EN mBIT(15)
6162 #define VXGE_HAL_DEBUG_CFG1_DIS_REL_OF_TAG_DUE_TO_ERR mBIT(11)
6166 #define VXGE_HAL_TEST_CFG1_PERR_INS_TX_WR_EP mBIT(19)
6167 #define VXGE_HAL_TEST_CFG1_PERR_INS_TX_RD_EP mBIT(23)
6168 #define VXGE_HAL_TEST_CFG1_PERR_INS_TX_CPL_EP mBIT(27)
6169 #define VXGE_HAL_TEST_CFG1_PERR_INS_TX_ECRCERR mBIT(31)
6170 #define VXGE_HAL_TEST_CFG1_PERR_INS_TX_LCRCERR mBIT(35)
6171 #define VXGE_HAL_TEST_CFG1_PERR_INS_RX_ECRCERR mBIT(39)
6172 #define VXGE_HAL_TEST_CFG1_PERR_INS_RX_LCRCERR mBIT(43)
6176 #define VXGE_HAL_TEST_CFG3_PERR_TRIGGER_TIMER mBIT(0)
6179 #define VXGE_HAL_WRCRDTARB_CFG0_STATS_PRTY_TIMEOUT_EN mBIT(55)
6180 #define VXGE_HAL_WRCRDTARB_CFG0_STATS_DROP_TIMEOUT_EN mBIT(59)
6181 #define VXGE_HAL_WRCRDTARB_CFG0_EN_XON mBIT(63)
6183 #define VXGE_HAL_WRCRDTARB_CFG1_RST_CREDIT mBIT(0)
6203 #define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT1_EN mBIT(3)
6204 #define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT2_EN mBIT(7)
6205 #define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT3_EN mBIT(11)
6206 #define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT4_EN mBIT(15)
6213 #define VXGE_HAL_RDCRDTARB_CFG0_EN_XON mBIT(63)
6215 #define VXGE_HAL_RDCRDTARB_CFG1_RST_CREDIT mBIT(0)
6234 #define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT1_EN mBIT(3)
6235 #define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT2_EN mBIT(7)
6236 #define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT3_EN mBIT(11)
6237 #define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT4_EN mBIT(15)
6250 #define VXGE_HAL_CLOCK_CFG0_ONE_LRO_EN mBIT(3)
6251 #define VXGE_HAL_CLOCK_CFG0_ONE_IWARP_EN mBIT(7)
6253 #define VXGE_HAL_STATS_BP_CTRL_WR_XON mBIT(7)
6255 #define VXGE_HAL_KDFCDMA_BP_CTRL_RD_XON mBIT(3)
6257 #define VXGE_HAL_INTCTL_BP_CTRL_WR_XON mBIT(3)
6272 #define VXGE_HAL_MRPCIM_SPI_CONTROL_SEL1 mBIT(4)
6273 #define VXGE_HAL_MRPCIM_SPI_CONTROL_NACK mBIT(5)
6274 #define VXGE_HAL_MRPCIM_SPI_CONTROL_DONE mBIT(6)
6275 #define VXGE_HAL_MRPCIM_SPI_CONTROL_REQ mBIT(7)
6282 #define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_HWPE mBIT(7)
6283 #define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SPI_16ADDR_EN mBIT(14)
6284 #define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SPI_2DEV_EN mBIT(15)
6285 #define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SLOWCK mBIT(63)
6293 #define VXGE_HAL_SW_RESET_STATUS_RESET_CMPLT mBIT(7)
6294 #define VXGE_HAL_SW_RESET_STATUS_INIT_CMPLT mBIT(15)
6298 #define VXGE_HAL_SW_RESET_CFG1_TYPE mBIT(0)
6303 #define VXGE_HAL_RIC_TIMEOUT_EN mBIT(3)
6309 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_RD_OR_WRN mBIT(39)
6311 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG2_REQ mBIT(0)
6313 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR mBIT(0)
6350 #define VXGE_HAL_MRPCIM_MMIO_CFG2_WRITE_CS mBIT(0)
6357 #define VXGE_HAL_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0 mBIT(3)
6358 #define VXGE_HAL_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2 mBIT(7)
6366 #define VXGE_HAL_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT mBIT(0)
6367 #define VXGE_HAL_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT mBIT(1)
6368 #define VXGE_HAL_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT mBIT(2)
6369 #define VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT mBIT(3)
6370 #define VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT mBIT(4)
6371 #define VXGE_HAL_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT mBIT(5)
6372 #define VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT mBIT(6)
6382 #define VXGE_HAL_GSTC_ERR0_REG_STC_CMCIF_RD_DATA_DB_ERR mBIT(26)
6393 #define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_REQ_FIFO_ERR mBIT(0)
6394 #define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_ECRESP_FIFO_ERR mBIT(1)
6395 #define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_BUFFRESP_FIFO_ERR mBIT(2)
6396 #define VXGE_HAL_GSTC_ERR1_REG_STC_H2L_EVENT_FIFO_ERR mBIT(3)
6397 #define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_RPE_FIFO_ERR mBIT(4)
6398 #define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_REQ_FIFO_ERR mBIT(5)
6399 #define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_EVENT_FIFO_ERR mBIT(6)
6400 #define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_CMRSP_FIFO_ERR mBIT(7)
6401 #define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_ARB_FIFO_ERR mBIT(8)
6402 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_EVENT_FIFO_ERR mBIT(9)
6403 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_FIFO_ERR mBIT(10)
6404 #define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_EVENT_FIFO_ERR mBIT(11)
6405 #define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_CMRSP_FIFO_ERR mBIT(12)
6406 #define VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_FIFO_ERR mBIT(13)
6407 #define VXGE_HAL_GSTC_ERR1_REG_STC_CP2STC_FIFO_ERR mBIT(14)
6408 #define VXGE_HAL_GSTC_ERR1_REG_STC_CPIF_CREDIT_FIFO_ERR mBIT(15)
6409 #define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_SHADOW_ERR mBIT(16)
6410 #define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_REQ_SHADOW_ERR mBIT(17)
6411 #define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_CTL_SHADOW_ERR mBIT(18)
6412 #define VXGE_HAL_GSTC_ERR1_REG_STC_SCC_SHADOW_ERR mBIT(19)
6413 #define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_SHADOW_ERR mBIT(20)
6414 #define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_SYNC_SHADOW_ERR mBIT(21)
6415 #define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_ARB_SHADOW_ERR mBIT(22)
6416 #define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_SYNC_SHADOW_ERR mBIT(23)
6417 #define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_EPE_SHADOW_ERR mBIT(24)
6418 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_SHADOW_ERR mBIT(25)
6419 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PSM_SHADOW_ERR mBIT(26)
6420 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PRC_SHADOW_ERR mBIT(27)
6421 #define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_SHADOW_ERR mBIT(28)
6422 #define VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_SHADOW_ERR mBIT(29)
6423 #define VXGE_HAL_GSTC_ERR1_REG_STC_CPIF_SHADOW_ERR mBIT(30)
6424 #define VXGE_HAL_GSTC_ERR1_REG_STC_SCC_CLM_ERR mBIT(32)
6425 #define VXGE_HAL_GSTC_ERR1_REG_STC_SCC_RMM_FSM_ERR mBIT(33)
6426 #define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_EPE_FSM_ERR mBIT(34)
6427 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_PBLESIZE0_ERR mBIT(35)
6428 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_QUOTIENT_ERR mBIT(36)
6429 #define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PRC_FSM_ERR mBIT(37)
6430 #define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_FSM_ERR mBIT(38)
6431 #define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_WRAP_ERR mBIT(39)
6432 #define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_BUFFER_ERR mBIT(40)
6433 #define VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_FSM_ERR mBIT(41)
6434 #define VXGE_HAL_GSTC_ERR1_REG_STC_UNK_CP_MSG_TYPE mBIT(42)
6442 #define VXGE_HAL_GH2L_ERR0_REG_H2L_RD_RSP_DB_ERR mBIT(8)
6445 #define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PA_DB_ERR mBIT(15)
6446 #define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PB_DB_ERR mBIT(16)
6453 #define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PA_SG_ERR mBIT(47)
6454 #define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PB_SG_ERR mBIT(48)
6458 #define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_WR_COMP_OFLOW_ERR mBIT(0)
6459 #define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_WR_COMP_UFLOW_ERR mBIT(1)
6460 #define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_CTL_OFLOW_ERR mBIT(2)
6461 #define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_CTL_UFLOW_ERR mBIT(3)
6462 #define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_OFLOW_ERR mBIT(4)
6463 #define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_UFLOW_ERR mBIT(5)
6464 #define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_DAT224_BB_OFLOW_ERR mBIT(6)
6465 #define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_DAT224_BB_UFLOW_ERR mBIT(7)
6466 #define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_REQ_OFLOW_ERR mBIT(8)
6467 #define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_REQ_UFLOW_ERR mBIT(9)
6468 #define VXGE_HAL_GHSQ_ERR_REG_H2L_WRDBL_OFLOW_ERR mBIT(10)
6469 #define VXGE_HAL_GHSQ_ERR_REG_H2L_WRDBL_UFLOW_ERR mBIT(11)
6470 #define VXGE_HAL_GHSQ_ERR_REG_H2L_HOC_XFER_DATX_UFLOW_ERR mBIT(12)
6471 #define VXGE_HAL_GHSQ_ERR_REG_H2L_HOC_XFER_CTLX_UFLOW_ERR mBIT(13)
6472 #define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_RSP_OFLOW_ERR mBIT(14)
6473 #define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_RSP_UFLOW_ERR mBIT(15)
6474 #define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_TRANS_POPCRDCNT_OFLOW_ERR mBIT(16)
6475 #define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_TRANS_POPCRDCNT_UFLOW_ERR mBIT(17)
6479 #define VXGE_HAL_GHSQ_ERR2_REG_H2L_OFLOW_ERR(n) mBIT(n)
6480 #define VXGE_HAL_GHSQ_ERR2_REG_H2L_UFLOW_ERR(n) mBIT(n)
6484 #define VXGE_HAL_GHSQ_ERR3_REG_H2L_OFLOW_ERR(n) mBIT(n)
6485 #define VXGE_HAL_GHSQ_ERR3_REG_H2L_UFLOW_ERR(n) mBIT(n)
6489 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_HOPIF_SM_ERR mBIT(0)
6490 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_NR_SM_ERR mBIT(1)
6491 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_HOF_SM_ERR mBIT(2)
6492 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_ROP_SM_ERR mBIT(3)
6493 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_OADE_SM_ERR mBIT(4)
6494 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_ODOG_SM_ERR mBIT(5)
6495 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR0 mBIT(6)
6496 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR1 mBIT(7)
6497 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR2 mBIT(8)
6498 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR3 mBIT(9)
6499 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR0 mBIT(10)
6500 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR1 mBIT(11)
6501 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR2 mBIT(12)
6502 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR3 mBIT(13)
6503 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR0 mBIT(14)
6504 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR1 mBIT(15)
6505 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR2 mBIT(16)
6506 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR3 mBIT(17)
6507 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR0 mBIT(18)
6508 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR1 mBIT(19)
6509 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR2 mBIT(20)
6510 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR3 mBIT(21)
6511 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR0 mBIT(22)
6512 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR1 mBIT(23)
6513 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR2 mBIT(24)
6514 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR3 mBIT(25)
6515 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_STAG_KILL_SM_ERROR mBIT(26)
6516 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_IMP_SM_ERROR mBIT(27)
6517 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_OMP_SM_ERROR mBIT(28)
6518 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_RECALL_SM_ERROR mBIT(29)
6519 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_LOG_CCTL_FIFO_ERR mBIT(30)
6520 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_RETXK_CCTL_FIFO_ERR mBIT(31)
6521 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HCC_HANDSHAKE_ERR mBIT(32)
6522 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_ARB_HANDSHAKE_ERR mBIT(33)
6523 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_RETXK_HANDSHAKE_ERR mBIT(34)
6524 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_OAE_HANDSHAKE_ERR mBIT(35)
6525 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_VPATH_ERR mBIT(36)
6526 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HO_SIZE_ERR mBIT(37)
6527 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HO_PARSE_ERR mBIT(38)
6528 #define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_ARB_SM_ERR mBIT(39)
6536 #define VXGE_HAL_HCC_ALARM_REG_H2L_CWBC_FSM_ERR mBIT(19)
6537 #define VXGE_HAL_HCC_ALARM_REG_H2L_RCC_FSM_ERR mBIT(23)
6541 #define VXGE_HAL_GSTC_CFG0_RPE_PF_ENA mBIT(7)
6542 #define VXGE_HAL_GSTC_CFG0_SCC_MODE mBIT(15)
6546 #define VXGE_HAL_GSTC_CFG0_INCL_ECI_FIFOS_PBL_SYNC mBIT(47)
6547 #define VXGE_HAL_GSTC_CFG0_MW_LOCAL_ACCESS_ENA mBIT(55)
6548 #define VXGE_HAL_GSTC_CFG0_LD_FW_CTRL_FIELDS mBIT(62)
6549 #define VXGE_HAL_GSTC_CFG0_ONLY_ROW0_DUSE1_WRITABLE mBIT(63)
6554 #define VXGE_HAL_GSTC_CFG1_BDM_EXTRA_RPE_PRM_RD mBIT(63)
6557 #define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_WIRE_INV mBIT(12)
6558 #define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_INV mBIT(13)
6559 #define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_DEALLOC mBIT(14)
6560 #define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_SUSP mBIT(15)
6561 #define VXGE_HAL_GSTC_CFG2_BDM_CACHE_ECC_ENABLE_N mBIT(16)
6562 #define VXGE_HAL_GSTC_CFG2_BDM_CMRSP_ECC_ENABLE_N mBIT(17)
6563 #define VXGE_HAL_GSTC_CFG2_ECI_CACHE0_ECC_ENABLE_N mBIT(18)
6564 #define VXGE_HAL_GSTC_CFG2_ECI_CACHE1_ECC_ENABLE_N mBIT(19)
6565 #define VXGE_HAL_GSTC_CFG2_H2L_EVENT_ECC_ENABLE_N mBIT(20)
6566 #define VXGE_HAL_GSTC_CFG2_PRM_EVENT_ECC_ENABLE_N mBIT(21)
6567 #define VXGE_HAL_GSTC_CFG2_SRCH_MEM_ECC_ENABLE_N mBIT(22)
6568 #define VXGE_HAL_GSTC_CFG2_GPSYNC_WAIT_TOKEN_ENABLE mBIT(29)
6569 #define VXGE_HAL_GSTC_CFG2_GPSYNC_CNTDOWN_TIMER_ENABLE mBIT(30)
6570 #define VXGE_HAL_GSTC_CFG2_GPSYNC_SRC_NOTIFY_ENABLE mBIT(31)
6618 #define VXGE_HAL_STC_SMI_ARB_CFG1_SAME_PRI_B2B_CAL mBIT(48)
6633 #define VXGE_HAL_STC_CAA_ARB_CFG1_SAME_PRI_B2B_CAL mBIT(39)
6649 #define VXGE_HAL_STC_ECI_CFG0_SUSPEND_DEALLOC_STAGS_ENA mBIT(4)
6650 #define VXGE_HAL_STC_ECI_CFG0_MULT_SUSPEND_ERR_ENA mBIT(5)
6651 #define VXGE_HAL_STC_ECI_CFG0_SUSPEND_PDID_CHECK_ENA mBIT(6)
6652 #define VXGE_HAL_STC_ECI_CFG0_UNSUSPEND_PDID_CHECK_ENA mBIT(7)
6653 #define VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_KEY_CHECK_ENA mBIT(14)
6654 #define VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_PDID_CHECK_ENA mBIT(15)
6655 #define VXGE_HAL_STC_ECI_CFG0_SET_SHARED_KEY_CHECK_ENA mBIT(23)
6656 #define VXGE_HAL_STC_ECI_CFG0_STAG_WR_FAIL_IF_DEALLOC mBIT(31)
6657 #define VXGE_HAL_STC_ECI_CFG0_PLACEMENT_MR_DEFERRAL_ENA mBIT(34)
6658 #define VXGE_HAL_STC_ECI_CFG0_SUSPEND_MR_DEFERRAL_ENA mBIT(35)
6659 #define VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_MR_DEFERRAL_ENA mBIT(36)
6660 #define VXGE_HAL_STC_ECI_CFG0_BIND_MW_MR_DEFERRAL_ENA mBIT(37)
6661 #define VXGE_HAL_STC_ECI_CFG0_SET_SHARED_MR_DEFERRAL_ENA mBIT(38)
6662 #define VXGE_HAL_STC_ECI_CFG0_STAG_WR_MR_DEFERRAL_ENA mBIT(39)
6664 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_PLACE_STALL_ENA mBIT(54)
6665 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_WIRE_INV_STALL_ENA mBIT(55)
6666 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_WIRE_INV_ENA mBIT(56)
6667 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_CP_INV_ENA mBIT(57)
6668 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_MR_EVENT_ENA mBIT(58)
6669 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_DEALLOC_ENA mBIT(59)
6670 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_ALTER_NUM_MWS_ENA mBIT(60)
6671 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_BIND_MW_ENA mBIT(61)
6672 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_SET_SHARED_ENA mBIT(62)
6673 #define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_STAG_WR_ENA mBIT(63)
6675 #define VXGE_HAL_STC_PRM_CFG0_PAC_RPE_PRI mBIT(6)
6676 #define VXGE_HAL_STC_PRM_CFG0_PAC_H2L_PRI mBIT(7)
6677 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL0_PRI mBIT(8)
6678 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL1_PRI mBIT(9)
6679 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL2_PRI mBIT(10)
6680 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL3_PRI mBIT(11)
6681 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL4_PRI mBIT(12)
6682 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL5_PRI mBIT(13)
6683 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL6_PRI mBIT(14)
6684 #define VXGE_HAL_STC_PRM_CFG0_PAC_CAL7_PRI mBIT(15)
6685 #define VXGE_HAL_STC_PRM_CFG0_PRC_RPE_PRI mBIT(22)
6686 #define VXGE_HAL_STC_PRM_CFG0_PRC_H2L_PRI mBIT(23)
6687 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL0_PRI mBIT(24)
6688 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL1_PRI mBIT(25)
6689 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL2_PRI mBIT(26)
6690 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL3_PRI mBIT(27)
6691 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL4_PRI mBIT(28)
6692 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL5_PRI mBIT(29)
6693 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL6_PRI mBIT(30)
6694 #define VXGE_HAL_STC_PRM_CFG0_PRC_CAL7_PRI mBIT(31)
6695 #define VXGE_HAL_STC_PRM_CFG0_RDUSE_ENA mBIT(39)
6697 #define VXGE_HAL_H2L_MISC_CFG_HSQ_FORCE_CMP mBIT(0)
6698 #define VXGE_HAL_H2L_MISC_CFG_HOP_IPID_MSB mBIT(1)
6699 #define VXGE_HAL_H2L_MISC_CFG_HOP_ARB_ENABLE mBIT(2)
6700 #define VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_HSN mBIT(3)
6701 #define VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_RD_XON mBIT(4)
6702 #define VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_PDA_VPBP mBIT(5)
6703 #define VXGE_HAL_H2L_MISC_CFG_OAE_VPBP_CHECK_ENA mBIT(6)
6704 #define VXGE_HAL_H2L_MISC_CFG_OAE_XON_CHECK_ENA mBIT(7)
6709 #define VXGE_HAL_H2L_MISC_CFG_HOC_DATX_ECC_ENABLE_N mBIT(35)
6710 #define VXGE_HAL_H2L_MISC_CFG_WRDBL_ECC_ENABLE_N mBIT(36)
6711 #define VXGE_HAL_H2L_MISC_CFG_WRBUF_ECC_ENABLE_N mBIT(37)
6712 #define VXGE_HAL_H2L_MISC_CFG_CMCRSP_ECC_ENABLE_N mBIT(38)
6713 #define VXGE_HAL_H2L_MISC_CFG_HOC_HEAD_ECC_ENABLE_N mBIT(39)
6714 #define VXGE_HAL_H2L_MISC_CFG_OD_MEM_ECC_ENABLE_N mBIT(40)
6715 #define VXGE_HAL_H2L_MISC_CFG_RW_CACHE_ECC_ENABLE_N mBIT(41)
6932 #define VXGE_HAL_PCMG3_INT_STATUS_DAM_ERR_DAM_INT mBIT(0)
6933 #define VXGE_HAL_PCMG3_INT_STATUS_PSTC_ERR_PSTC_INT mBIT(1)
6934 #define VXGE_HAL_PCMG3_INT_STATUS_PH2L_ERR0_PH2L_INT mBIT(2)
6937 #define VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_SG_ERR mBIT(0)
6938 #define VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_SG_ERR mBIT(1)
6939 #define VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_SG_ERR mBIT(3)
6940 #define VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_SG_ERR mBIT(4)
6941 #define VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_SG_ERR mBIT(5)
6942 #define VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_DB_ERR mBIT(32)
6943 #define VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_DB_ERR mBIT(33)
6944 #define VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_DB_ERR mBIT(34)
6945 #define VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_DB_ERR mBIT(35)
6946 #define VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_DB_ERR mBIT(36)
6947 #define VXGE_HAL_DAM_ERR_REG_DAM_HPRD_ERR mBIT(40)
6948 #define VXGE_HAL_DAM_ERR_REG_DAM_LPRD_0_ERR mBIT(41)
6949 #define VXGE_HAL_DAM_ERR_REG_DAM_LPRD_1_ERR mBIT(42)
6950 #define VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_OVERFLOW_ERR mBIT(48)
6951 #define VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_OVERFLOW_ERR mBIT(49)
6952 #define VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_OVERFLOW_ERR mBIT(50)
6953 #define VXGE_HAL_DAM_ERR_REG_DAM_SM_ERR mBIT(56)
6957 #define VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_REQ_FIFO_ERR mBIT(0)
6958 #define VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_ECRESP_FIFO_ERR mBIT(1)
6959 #define VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_BUFFRESP_FIFO_ERR mBIT(2)
6960 #define VXGE_HAL_PSTC_ERR_REG_STC_ARB_RPE_FIFO_ERR mBIT(3)
6961 #define VXGE_HAL_PSTC_ERR_REG_STC_CP2STC_FIFO_ERR mBIT(4)
6965 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_DATX_OFLOW_ERR mBIT(0)
6966 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_CTLX_OFLOW_ERR mBIT(1)
6967 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_PARSE_ERR mBIT(2)
6968 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_TCPOP_BYTES_ERR mBIT(3)
6969 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_IDATA_BYTES_ERR mBIT(4)
6970 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_PLDTYPE_ERR mBIT(5)
6971 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_OD_ODLIST_LEN_ERR mBIT(6)
6972 #define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_VPATH_ERR mBIT(7)
6976 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TBL_DB_ERR mBIT(15)
6977 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_FIFO_ERR mBIT(16)
6978 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_CCTL_FIFO_ERR mBIT(17)
6979 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_FIFO_ERR mBIT(18)
6980 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_CRED_CNT_ERR mBIT(19)
6981 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PDI_CRED_CNT_ERR mBIT(20)
6982 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PCTL_SHADOW_ERR mBIT(21)
6983 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_OPC_SHADOW_ERR mBIT(22)
6984 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_SHADOW_ERR mBIT(23)
6985 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PDI_SHADOW_ERR mBIT(24)
6986 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_LCTL_SHADOW_ERR mBIT(26)
6987 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TXI_SHADOW_ERR mBIT(27)
6988 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_RXI_SHADOW_ERR mBIT(28)
6989 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_HPI_SHADOW_ERR mBIT(29)
6990 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_SHADOW_ERR mBIT(30)
6991 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PCTL_FSM_ERR mBIT(31)
6992 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_FSM_ERR mBIT(32)
6993 #define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_LO_COMPL_ERR mBIT(33)
6994 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_LCTL_FSM_ERR mBIT(34)
6995 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TXI_FSM_ERR mBIT(35)
6996 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_SLOT_MGMT_ERR mBIT(36)
6997 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_HPI_FSM_ERR mBIT(37)
6998 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_FSM_ERR mBIT(38)
6999 #define VXGE_HAL_PH2L_ERR0_REG_H2L_ROCRC_HOP_OFLOW_ERR mBIT(39)
7000 #define VXGE_HAL_PH2L_ERR0_REG_H2L_PDA_H2L_DONE_FIFO_OVERFLOW mBIT(40)
7004 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TBL_SG_ERR mBIT(55)
7008 #define VXGE_HAL_DAM_BYPASS_QUEUE_0_ENABLE mBIT(0)
7018 #define VXGE_HAL_DAM_ECC_CTRL_DISABLE mBIT(0)
7020 #define VXGE_HAL_PH2L_CFG0_PHDR_MEM_ECC_ENABLE_N mBIT(15)
7021 #define VXGE_HAL_PH2L_CFG0_IDATA_MEM_ECC_ENABLE_N mBIT(23)
7022 #define VXGE_HAL_PH2L_CFG0_RO_CACHE_ECC_ENABLE_N mBIT(31)
7023 #define VXGE_HAL_PH2L_CFG0_RETXK_TBL_ECC_ENABLE_N mBIT(39)
7024 #define VXGE_HAL_PH2L_CFG0_LOG_XON_CHECK_ENA mBIT(47)
7025 #define VXGE_HAL_PH2L_CFG0_LOG_VPBP_CHECK_ENA mBIT(55)
7028 #define VXGE_HAL_PSTC_CFG0_PGSYNC_WAIT_TOKEN_ENABLE mBIT(5)
7029 #define VXGE_HAL_PSTC_CFG0_PGSYNC_CNTDOWN_TIMER_ENABLE mBIT(6)
7030 #define VXGE_HAL_PSTC_CFG0_PGSYNC_SRC_NOTIFY_ENABLE mBIT(7)
7035 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG1 mBIT(0)
7036 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG2 mBIT(1)
7037 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG3 mBIT(2)
7038 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_DRBELL mBIT(3)
7039 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_FBIF mBIT(4)
7040 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_MSG mBIT(5)
7041 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_ONE mBIT(6)
7042 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_PCI mBIT(7)
7043 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_RTDMA mBIT(8)
7044 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_WRDMA mBIT(9)
7045 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_XGMAC mBIT(10)
7046 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_FB mBIT(11)
7047 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CM mBIT(12)
7048 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_OVERRIDE_FB_DONE mBIT(16)
7049 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_OVERRIDE_CM_DONE mBIT(17)
7050 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_INCLUDE_PCIE_MEMS mBIT(24)
7051 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_LAUNCH mBIT(31)
7052 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_DONE mBIT(48)
7066 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_FB mBIT(33)
7067 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CM mBIT(34)
8925 #define VXGE_HAL_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT mBIT(0)
8928 #define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK mBIT(6)
8929 #define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR mBIT(7)
8931 #define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT mBIT(55)
8937 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_ROLL mBIT(23)
8939 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_ENABLE mBIT(39)
8942 #define VXGE_HAL_G3IFCMD_FB_IO_CTRL_DRIVE mBIT(7)
8956 #define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_TRA_START mBIT(6)
8957 #define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_TRA_DISABLE mBIT(7)
8969 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_ROLL mBIT(7)
8970 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_ENABLE mBIT(14)
8971 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
8978 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_ROLL mBIT(7)
8979 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_DLL_ENABLE mBIT(15)
8981 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
9012 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9017 mBIT(7)
9019 mBIT(15)
9021 mBIT(23)
9023 mBIT(31)
9024 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9025 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9061 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23)
9074 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_ROLL mBIT(7)
9075 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_ENABLE mBIT(14)
9076 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9083 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_ROLL mBIT(7)
9084 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_DLL_ENABLE mBIT(15)
9086 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
9117 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9121 mBIT(7)
9123 mBIT(15)
9125 mBIT(23)
9127 mBIT(31)
9128 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9129 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9164 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23)
9174 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_ROLL mBIT(7)
9175 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_ENABLE mBIT(14)
9176 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9183 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_ROLL mBIT(7)
9184 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_DLL_ENABLE mBIT(15)
9186 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
9217 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9222 mBIT(7)
9224 mBIT(15)
9226 mBIT(23)
9228 mBIT(31)
9229 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9230 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9265 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23)
9273 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_ROLL mBIT(7)
9274 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_ENABLE mBIT(14)
9275 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9282 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_ROLL mBIT(7)
9283 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_DLL_ENABLE mBIT(15)
9285 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
9316 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9320 mBIT(7)
9322 mBIT(15)
9324 mBIT(23)
9326 mBIT(31)
9327 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9328 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9363 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23)
9367 #define VXGE_HAL_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT mBIT(0)
9370 #define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK mBIT(6)
9371 #define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR mBIT(7)
9373 #define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT mBIT(55)
9379 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_ROLL mBIT(23)
9381 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_ENABLE mBIT(39)
9384 #define VXGE_HAL_G3IFCMD_CMU_IO_CTRL_DRIVE mBIT(7)
9398 #define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_TRA_START mBIT(6)
9399 #define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_TRA_DISABLE mBIT(7)
9411 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_ROLL mBIT(7)
9412 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_ENABLE mBIT(14)
9413 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9420 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_ROLL mBIT(7)
9421 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_DLL_ENABLE mBIT(15)
9424 mBIT(31)
9455 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9460 mBIT(7)
9462 mBIT(15)
9464 mBIT(23)
9466 mBIT(31)
9467 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9468 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9503 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23)
9511 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_ROLL mBIT(7)
9512 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_ENABLE mBIT(14)
9513 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9520 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_ROLL mBIT(7)
9521 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_DLL_ENABLE mBIT(15)
9523 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
9554 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9559 mBIT(7)
9561 mBIT(15)
9563 mBIT(23)
9565 mBIT(31)
9566 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9567 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9602 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23)
9612 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_ROLL mBIT(7)
9613 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_ENABLE mBIT(14)
9614 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9621 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_ROLL mBIT(7)
9623 mBIT(15)
9627 mBIT(31)
9658 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9663 mBIT(7)
9665 mBIT(15)
9667 mBIT(23)
9669 mBIT(31)
9670 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9671 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9706 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23)
9714 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_ROLL mBIT(7)
9715 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_ENABLE mBIT(14)
9716 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9723 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_ROLL mBIT(7)
9724 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_DLL_ENABLE mBIT(15)
9726 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
9758 mBIT(23)
9763 mBIT(7)
9765 mBIT(15)
9767 mBIT(23)
9769 mBIT(31)
9770 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9771 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9806 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23)
9810 #define VXGE_HAL_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT mBIT(0)
9813 #define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK mBIT(6)
9814 #define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR mBIT(7)
9817 #define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT mBIT(55)
9823 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_ROLL mBIT(23)
9825 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_ENABLE mBIT(39)
9828 #define VXGE_HAL_G3IFCMD_CML_IO_CTRL_DRIVE mBIT(7)
9846 #define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_TRA_START mBIT(6)
9847 #define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_TRA_DISABLE mBIT(7)
9861 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_ROLL mBIT(7)
9862 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_ENABLE mBIT(14)
9863 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9870 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_ROLL mBIT(7)
9871 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_DLL_ENABLE mBIT(15)
9874 mBIT(31)
9905 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23)
9910 mBIT(7)
9912 mBIT(15)
9914 mBIT(23)
9916 mBIT(31)
9917 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
9918 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
9953 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23)
9961 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_ROLL mBIT(7)
9962 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_ENABLE mBIT(14)
9963 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
9970 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_ROLL mBIT(7)
9971 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_DLL_ENABLE mBIT(15)
9973 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
10004 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_DISABLE mBIT(23)
10009 mBIT(7)
10011 mBIT(15)
10013 mBIT(23)
10015 mBIT(31)
10016 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
10017 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
10053 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23)
10063 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_ROLL mBIT(7)
10064 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_ENABLE mBIT(14)
10065 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
10072 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_ROLL mBIT(7)
10073 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_DLL_ENABLE mBIT(15)
10076 mBIT(31)
10107 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23)
10112 mBIT(7)
10114 mBIT(15)
10116 mBIT(23)
10118 mBIT(31)
10119 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
10120 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
10155 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23)
10163 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_ROLL mBIT(7)
10164 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_ENABLE mBIT(14)
10165 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
10172 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_ROLL mBIT(7)
10173 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_DLL_ENABLE mBIT(15)
10175 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
10206 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_DISABLE mBIT(23)
10211 mBIT(7)
10213 mBIT(15)
10215 mBIT(23)
10217 mBIT(31)
10218 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
10219 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
10254 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23)
10264 #define VXGE_HAL_XGXS_CFG_PORT_SEL_INFO_0 mBIT(27)
10288 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR mBIT(23)
10297 #define VXGE_HAL_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES mBIT(3)
10305 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE0 mBIT(16)
10306 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE1 mBIT(17)
10307 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE2 mBIT(18)
10308 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE3 mBIT(19)
10309 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE0 mBIT(20)
10310 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE1 mBIT(21)
10311 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE2 mBIT(22)
10312 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE3 mBIT(23)
10313 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE0 mBIT(24)
10314 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE1 mBIT(25)
10315 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE2 mBIT(26)
10316 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE3 mBIT(27)
10317 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_MPLL_CK_OFF mBIT(31)
10318 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_MPLL_PWRON mBIT(35)
10320 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RESET_N mBIT(43)
10321 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_READY mBIT(47)
10322 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE0 mBIT(48)
10323 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE1 mBIT(49)
10324 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE2 mBIT(50)
10325 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE3 mBIT(51)
10326 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TRUST_HW_RX_CK_READY mBIT(55)
10336 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE0 mBIT(32)
10337 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE1 mBIT(33)
10338 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE2 mBIT(34)
10339 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE3 mBIT(35)
10340 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE0 mBIT(36)
10341 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE1 mBIT(37)
10342 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE2 mBIT(38)
10343 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE3 mBIT(39)
10344 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE0 mBIT(40)
10345 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE1 mBIT(41)
10346 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE2 mBIT(42)
10347 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE3 mBIT(43)
10354 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE0 mBIT(0)
10355 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE1 mBIT(1)
10356 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE2 mBIT(2)
10357 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE3 mBIT(3)
10371 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE0 mBIT(0)
10372 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE1 mBIT(1)
10373 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE2 mBIT(2)
10374 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE3 mBIT(3)
10379 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_WIDE_XFACE mBIT(14)
10380 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_RTUNE_DO_TUNE mBIT(15)
10383 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_SS_EN mBIT(32)
10395 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE0 mBIT(8)
10396 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE1 mBIT(9)
10397 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE2 mBIT(10)
10398 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE3 mBIT(11)
10399 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE0 mBIT(12)
10400 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE1 mBIT(13)
10401 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE2 mBIT(14)
10402 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE3 mBIT(15)
10403 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE0 mBIT(16)
10404 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE1 mBIT(17)
10405 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE2 mBIT(18)
10406 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE3 mBIT(19)
10407 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE0 mBIT(20)
10408 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE1 mBIT(21)
10409 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE2 mBIT(22)
10410 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE3 mBIT(23)
10411 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE0 mBIT(24)
10412 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE1 mBIT(25)
10413 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE2 mBIT(26)
10414 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE3 mBIT(27)
10415 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_OP_DONE_ASSERTED mBIT(30)
10416 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_OP_DONE_DEASSERTED mBIT(31)
10417 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_POWER_GOOD mBIT(35)
10418 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_SERDES_INIT_COMPLETE mBIT(39)
10420 #define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_WE mBIT(3)
10421 #define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_STROBE mBIT(7)
10431 #define VXGE_HAL_RATEMGMT_CFG_PORT_RATE mBIT(7)
10432 #define VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM mBIT(11)
10433 #define VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM mBIT(15)
10434 #define VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM mBIT(19)
10436 #define VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE mBIT(3)
10437 #define VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_RATE mBIT(7)
10438 #define VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY mBIT(11)
10442 #define VXGE_HAL_RATEMGMT_FIXED_CFG_PORT_RESTART mBIT(7)
10444 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_RESTART mBIT(7)
10445 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY mBIT(11)
10446 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL mBIT(15)
10453 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G mBIT(31)
10454 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G mBIT(35)
10456 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_RESTART mBIT(7)
10457 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE mBIT(11)
10458 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE mBIT(15)
10462 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4 mBIT(31)
10463 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX mBIT(35)
10469 #define VXGE_HAL_ANBE_MGR_CTRL_PORT_WE mBIT(3)
10470 #define VXGE_HAL_ANBE_MGR_CTRL_PORT_STROBE mBIT(7)
10476 #define VXGE_HAL_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES mBIT(3)
10477 #define VXGE_HAL_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES mBIT(7)
10480 mBIT(3)
10482 mBIT(7)
10484 mBIT(11)
10486 mBIT(15)
10490 mBIT(27)
10492 mBIT(31)
10494 mBIT(35)
10496 mBIT(39)
10498 mBIT(43)
10500 mBIT(47)
10502 mBIT(51)
10504 mBIT(55)
10510 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE mBIT(32)
10511 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY mBIT(33)
10512 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE mBIT(40)
10513 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE mBIT(41)
10514 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE mBIT(42)
10517 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP mBIT(48)
10518 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK mBIT(49)
10519 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT mBIT(50)
10520 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR mBIT(51)
10521 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE mBIT(53)
10535 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G mBIT(3)
10536 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G mBIT(7)
10539 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_TIMEOUT mBIT(19)
10540 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE mBIT(23)
10542 mBIT(27)
10543 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP mBIT(31)
10545 mBIT(35)
10547 mBIT(39)
10548 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD mBIT(43)
10549 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD mBIT(47)
10551 mBIT(51)
10552 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE mBIT(55)
10553 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN mBIT(59)
10555 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP mBIT(0)
10556 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK mBIT(1)
10557 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF mBIT(2)
10558 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP mBIT(3)
10564 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP mBIT(0)
10565 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK mBIT(1)
10566 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP mBIT(2)
10567 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2 mBIT(3)
10568 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE mBIT(4)
10576 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE mBIT(3)
10582 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_PREAMBLE mBIT(51)
10584 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO mBIT(63)