dev/vx/if_vx.c

163 	CSR_WRITE_2(sc, VX_COMMAND, GLOBAL_RESET);
180 		CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD
239 	CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);
241 	CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);
248 	CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
250 	CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
259 	CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | 0xff);
264 	CSR_WRITE_2(sc, VX_COMMAND, RX_ENABLE);
265 	CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);
285 	CSR_WRITE_2(sc, VX_COMMAND, SET_RX_FILTER |
394 	CSR_WRITE_2(sc, VX_COMMAND, STOP_TRANSCEIVER);
397 	CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, 0);
403 		CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, ENABLE_UTP);
406 		CSR_WRITE_2(sc, VX_COMMAND, START_TRANSCEIVER);
412 		CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, LINKBEAT_ENABLE);
473 		CSR_WRITE_2(sc, VX_COMMAND,
482 	CSR_WRITE_2(sc, VX_COMMAND, SET_TX_AVAIL_THRESH | (8188 >> 2));
488 	CSR_WRITE_2(sc, VX_COMMAND, SET_TX_START_THRESH |
630 			CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);
646 		CSR_WRITE_2(sc, VX_COMMAND, C_INTR_LATCH);
660 		CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | status);
801 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);
886 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);
1000 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISABLE);
1001 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);
1003 	CSR_WRITE_2(sc, VX_COMMAND, TX_DISABLE);
1004 	CSR_WRITE_2(sc, VX_COMMAND, STOP_TRANSCEIVER);
1006 	CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);
1008 	CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);
1010 	CSR_WRITE_2(sc, VX_COMMAND, C_INTR_LATCH);
1011 	CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK);
1012 	CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK);
1013 	CSR_WRITE_2(sc, VX_COMMAND, SET_RX_FILTER);