Lines Matching refs:CSR_WRITE_2
178 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
202 CSR_WRITE_2(sc, VTE_MMWD, val);
203 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
259 CSR_WRITE_2(sc, VTE_MRICR, val);
267 CSR_WRITE_2(sc, VTE_MTICR, val);
1159 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1255 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1356 CSR_WRITE_2(sc, VTE_MIER, 0);
1377 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1576 CSR_WRITE_2(sc, VTE_MRDCR, prog |
1608 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1621 CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
1622 CSR_WRITE_2(sc, VTE_MACSM, 0);
1679 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
1680 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
1681 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
1685 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
1686 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
1689 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
1690 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
1697 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
1710 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
1713 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
1724 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
1731 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
1738 CSR_WRITE_2(sc, VTE_MRICR, 0);
1739 CSR_WRITE_2(sc, VTE_MTICR, 0);
1742 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
1747 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1748 CSR_WRITE_2(sc, VTE_MISR, 0);
1779 CSR_WRITE_2(sc, VTE_MIER, 0);
1780 CSR_WRITE_2(sc, VTE_MECIER, 0);
1834 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1860 CSR_WRITE_2(sc, VTE_MCR0, mcr);
2024 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]);
2025 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]);
2026 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]);
2027 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]);
2030 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
2032 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
2034 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
2037 CSR_WRITE_2(sc, VTE_MCR0, mcr);