Lines Matching defs:divisor
1454 uint32_t clk, divisor, fastclk_flag, frac, hwspeed;
1470 * and a 14-bit divisor.
1476 * Calculate the divisor, initially yielding a fixed point number with a
1478 * hardware can handle. When the integral part of the divisor is
1483 * If the integral part of the divisor is 1, a special rule applies: the
1497 divisor = (clk << 4) / speed;
1498 if ((divisor & 0xf) == 1)
1499 divisor &= 0xfffffff8;
1501 divisor += roundoff_232a[divisor & 0x0f];
1503 divisor += 1; /* Rounds odd 16ths up to next 8th. */
1504 divisor >>= 1;
1510 hwspeed = (clk << 3) / divisor;
1515 * Re-pack the divisor into hardware format. The lower 14-bits hold the
1523 * When the divisor is 1 a special encoding applies: 1.0 is encoded as
1527 frac = divisor & 0x07;
1528 divisor >>= 3;
1529 if (divisor == 1) {
1531 divisor = 0; /* 1.0 becomes 0.0 */
1535 divisor |= (encoded_fraction[frac] << 14) | fastclk_flag;
1537 cfg->baud_lobits = (uint16_t)divisor;
1538 cfg->baud_hibits = (uint16_t)(divisor >> 16);