Lines Matching refs:CSR_WRITE_2
277 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
279 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
283 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
291 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
297 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
303 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
326 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
443 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
493 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
499 CSR_WRITE_2(sc, DATA_REG_W, 0);
532 CSR_WRITE_2(sc, DATA_REG_W, 0);
543 CSR_WRITE_2(sc, DATA_REG_W, 0);
553 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
685 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
692 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
698 CSR_WRITE_2(sc, DATA_REG_W, 0);
730 CSR_WRITE_2(sc, DATA_REG_W, 0);
741 CSR_WRITE_2(sc, DATA_REG_W, 0);
750 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
887 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
913 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
915 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
924 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
1027 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1115 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1201 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1202 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1304 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1319 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1341 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1392 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1394 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1396 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1398 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1405 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);