dev/siba/siba_core.c

1935 siba_pcicore_init(struct siba_pci *spc)
1937 	struct siba_dev_softc *sd = spc->spc_dev;
1945 	KASSERT(spc->spc_hostmode == 0,
1948 	siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0);
2084 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
2086 	struct siba_dev_softc *psd = spc->spc_dev;
2091 		siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2,
2092 		    siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) |
2114 			tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
2116 			siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp);
2121 			siba_pcie_write(spc, 0x4,
2122 			    siba_pcie_read(spc, 0x4) | 0x8);
2124 			siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */
2125 			siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */
2126 			siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */
2128 			siba_pcie_write(spc, 0x100,
2129 			    siba_pcie_read(spc, 0x100) | 0x40);
2131 	spc->spc_inited = 1;
2139 	struct siba_pci *spc = &siba->siba_pci;
2140 	struct siba_dev_softc *psd = spc->spc_dev;
2163 	if (spc->spc_inited == 0)
2164 		siba_pcicore_setup(spc, sd);
2168 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset)
2171 	return (siba_read_4_sub(spc->spc_dev, offset));
2175 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value)
2178 	siba_write_4_sub(spc->spc_dev, offset, value);
2182 siba_pcie_read(struct siba_pci *spc, uint32_t address)
2185 	siba_pcicore_write_4(spc, 0x130, address);
2186 	return (siba_pcicore_read_4(spc, 0x134));
2190 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data)
2193 	siba_pcicore_write_4(spc, 0x130, address);
2194 	siba_pcicore_write_4(spc, 0x134, data);
2198 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address,
2203 	siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2);
2204 	siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA,
2210 		if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100)
2214 	siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0);