Lines Matching defs:encp
135 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
165 &encp->enc_external_port)) != 0)
177 encp->enc_pf = pf;
178 encp->enc_vf = vf;
181 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
205 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
217 encp->enc_board_type = board_type;
218 encp->enc_clk_mult = 1; /* not used for Medford */
247 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
252 encp->enc_bug41750_workaround = B_TRUE;
256 encp->enc_bug26807_workaround = B_TRUE;
266 encp->enc_bug61265_workaround = B_TRUE;
268 encp->enc_bug61265_workaround = B_FALSE;
280 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
281 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
289 encp->enc_rx_buf_align_start = 1;
294 encp->enc_rx_buf_align_end = end_padding;
297 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
305 encp->enc_evq_limit = 1024;
306 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
307 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
309 encp->enc_buftbl_limit = 0xFFFFFFFF;
311 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
312 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
313 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
323 encp->enc_privilege_mask = mask;
327 if (EFX_PCI_FUNCTION_IS_PF(encp))
334 encp->enc_intr_vec_base = base;
335 encp->enc_intr_limit = nvec;
341 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
347 encp->enc_vpd_is_global = B_TRUE;
352 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
353 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;