sfxge/common/hunt_nic.c

52 	efx_rc_t rc;
60 	if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
71 		if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
84 		if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
97 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
99 	return (rc);
120 	efx_rc_t rc;
122 	if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
131 	if ((rc = ef10_external_port_mapping(enp, port,
141 	if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
149 		rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
150 		if ((rc == 0) && (mac_addr[0] & 0x02)) {
157 			rc = EINVAL;
160 		rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
162 	if (rc != 0)
168 	rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
169 	if (rc != 0) {
171 		if (rc == EACCES)
181 	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
185 	if ((rc = ef10_phy_get_link(enp, &els)) != 0)
210 	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
212 	if ((rc == 0) || (rc == EACCES))
214 	else if ((rc == ENOTSUP) || (rc == ENOENT))
223 	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
225 	if (rc == 0) {
227 	} else if (rc == EACCES) {
233 	} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
252 	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
254 	if (rc == 0) {
265 	} else if (rc == EACCES) {
271 	} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
278 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
297 	if ((rc = ef10_get_datapath_caps(enp)) != 0)
329 	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
334 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
351 	if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
389 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
391 	return (rc);