sfxge/common/hunt_nic.c

107 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
132 		    &encp->enc_external_port)) != 0)
144 	encp->enc_pf = pf;
145 	encp->enc_vf = vf;
148 	if (EFX_PCI_FUNCTION_IS_PF(encp)) {
165 	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
177 	encp->enc_board_type = board_type;
178 	encp->enc_clk_mult = 1; /* not used for Huntington */
213 		encp->enc_bug35388_workaround = B_TRUE;
215 		encp->enc_bug35388_workaround = B_FALSE;
226 		encp->enc_bug41750_workaround = B_TRUE;
230 			encp->enc_bug41750_workaround = B_TRUE;
232 			encp->enc_bug41750_workaround = B_FALSE;
234 		encp->enc_bug41750_workaround = B_FALSE;
238 	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
240 		encp->enc_bug41750_workaround = B_TRUE;
255 		encp->enc_bug26807_workaround = B_TRUE;
270 		encp->enc_bug26807_workaround = B_FALSE;
272 		encp->enc_bug26807_workaround = B_FALSE;
285 	encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
286 	if (encp->enc_bug35388_workaround) {
287 		encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
290 		encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
294 	encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
301 	encp->enc_rx_buf_align_start = 1;
302 	encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
305 	encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
313 	encp->enc_evq_limit = 1024;
314 	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
315 	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
317 	encp->enc_buftbl_limit = 0xFFFFFFFF;
319 	encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
320 	encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
321 	encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
331 	encp->enc_privilege_mask = mask;
335 		if (EFX_PCI_FUNCTION_IS_PF(encp))
342 	encp->enc_intr_vec_base = base;
343 	encp->enc_intr_limit = nvec;
349 	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
353 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
356 	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;