sfxge/common/efx_nic.c

117 	efx_rc_t rc;
133 		rc = EIO;
139 		rc = EIO;
156 		rc = EIO;
162 		rc = EIO;
175 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
177 	return (rc);
247 	efx_rc_t rc;
256 		rc = ENOMEM;
316 		rc = ENOTSUP;
338 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
340 	return (rc);
348 	efx_rc_t rc;
357 	if ((rc = enop->eno_probe(enp)) != 0)
360 	if ((rc = efx_phy_probe(enp)) != 0)
373 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
375 	return (rc);
384 	efx_rc_t rc;
390 		if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
397 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
399 	return (rc);
410 	efx_rc_t rc;
417 		rc = ENOTSUP;
420 	if ((rc = (enop->eno_get_bar_region)(enp,
431 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
433 	return (rc);
446 	efx_rc_t rc;
455 		if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
471 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
473 	return (rc);
482 	efx_rc_t rc;
488 		rc = EINVAL;
492 	if ((rc = enop->eno_init(enp)) != 0)
502 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
504 	return (rc);
578 	efx_rc_t rc;
596 		rc = EINVAL;
600 	if ((rc = enop->eno_reset(enp)) != 0)
608 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
610 	return (rc);
629 	efx_rc_t rc;
635 	if ((rc = enop->eno_register_test(enp)) != 0)
641 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
643 	return (rc);
656 	efx_rc_t rc;
682 				rc = EIO;
697 				rc = EIO;
715 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
720 	return (rc);
735 	efx_rc_t rc;
760 				rc = EIO;
774 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
776 	return (rc);
895 	efx_rc_t rc;
907 		rc = req.emr_rc;
914 		rc = EMSGSIZE;
962 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
964 	return (rc);
977 	efx_rc_t rc;
981 		rc = EINVAL;
999 		rc = EINVAL;
1011 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
1013 	return (rc);
1027 	efx_rc_t rc;
1042 	rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1044 	if (rc != 0)
1062 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
1064 	return (rc);