sfxge/common/ef10_nic.c

853 	efx_nic_cfg_t *encp = &enp->en_nic_cfg;
872 	blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
962 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
984 	encp->enc_rx_prefix_size = 14;
987 	encp->enc_fw_assisted_tso_enabled =
991 	encp->enc_fw_assisted_tso_v2_enabled =
995 	encp->enc_datapath_cap_evb =
999 	encp->enc_hw_tx_insert_vlan_enabled =
1003 	encp->enc_rx_batching_enabled =
1010 	encp->enc_rx_batch_max = 16;
1013 	encp->enc_rx_disable_scatter_supported =
1017 	encp->enc_allow_set_mac_with_installed_filters =
1025 	encp->enc_enhanced_set_mac_supported =
1032 	encp->enc_init_evq_v2_supported =
1070 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1074 	if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1080 		if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1214 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1245 	    MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1270 	encp->enc_features = enp->en_features;
1303 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1316 	min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1317 	min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1318 	min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1323 	max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1324 	max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1325 	max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1334 	if ((encp->enc_piobuf_size == 0) ||
1335 	    (encp->enc_piobuf_limit == 0) ||
1337 	    (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1346 			    encp->enc_piobuf_min_alloc_size);
1348 		blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1351 		blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);