dev/rtwn/if_rtwn.c

121 static uint8_t	rtwn_read_1(struct rtwn_softc *, uint16_t);
827 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr)
855 		if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
1175 	    rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1178 	    rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1189 	    rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1198 		reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1261 		    rtwn_read_1(sc, R92C_BCN_CTRL) |
1281 		    rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1911 		if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
1994 	    rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL);
1996 	reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
2004 	reg = rtwn_read_1(sc, R92C_APSD_CTRL);
2006 	    rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
2008 		if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
2157 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
2165 	    rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
2167 	    rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
2171 	    rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
2182 	    rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
2475 		reg = rtwn_read_1(sc, 0x16);
2807 		    rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
2809 		reg = rtwn_read_1(sc, R92C_RRSR + 2);
2842 		    rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
2947 		iq_cal_regs.txpause = rtwn_read_1(sc, R92C_TXPAUSE);
2948 		iq_cal_regs.bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL);
2949 		iq_cal_regs.ustime_tsf = rtwn_read_1(sc, R92C_USTIME_TSF);
3200 	txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
3396 	    rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
3441 	reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN);
3452 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)