dev/rp/rp_isa.c

76 Call:	  sControllerEOI(MudbacCtlP,CtlP)
78 	  CONTROLLER_T *CtlP; Ptr to controller structure
80 #define sControllerEOI(MudbacCtlP,CtlP) \
81 	rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2 | INT_STROB)
86 Call:	  sDisAiop(MudbacCtlP,CtlP)
88 	  CONTROLLER_T *CtlP; Ptr to controller structure
91 #define sDisAiop(MudbacCtlP,CtlP,AIOPNUM) \
93    ISACTL(CtlP)->MReg3 &= rp_sBitMapClrTbl[AIOPNUM]; \
94    rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
100 Call:	  sEnAiop(MudbacCtlP,CtlP)
102 	  CONTROLLER_T *CtlP; Ptr to controller structure
105 #define sEnAiop(MudbacCtlP,CtlP,AIOPNUM) \
107    ISACTL(CtlP)->MReg3 |= rp_sBitMapSetTbl[AIOPNUM]; \
108    rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
114 Call:	  sGetControllerIntStatus(MudbacCtlP,CtlP)
116 	  CONTROLLER_T *CtlP; Ptr to controller structure
123 #define sGetControllerIntStatus(MudbacCtlP,CtlP) \
124 	(rp_readio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg1IO) & 0x0f)
133 static int sInitController(CONTROLLER_T *CtlP,
303 Call:	  sInitController(CtlP,MudbacCtlP,AiopNum,
305 	  CONTROLLER_T *CtlP; Ptr to controller structure
365 sInitController(	CONTROLLER_T *CtlP,
375 	CtlP->CtlID = CTLID_0001;		/* controller release 1 */
377 	ISACTL(CtlP)->MBaseIO = rp_nisadevs;
378 	if (MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] != NULL) {
379 		ISACTL(CtlP)->MReg0IO = 0x40 + 0;
380 		ISACTL(CtlP)->MReg1IO = 0x40 + 1;
381 		ISACTL(CtlP)->MReg2IO = 0x40 + 2;
382 		ISACTL(CtlP)->MReg3IO = 0x40 + 3;
384 		MudbacCtlP->io_rid[ISACTL(CtlP)->MBaseIO] = ISACTL(CtlP)->MBaseIO;
386 		MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] = bus_alloc_resource(MudbacCtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[ISACTL(CtlP)->MBaseIO], ctl_base, ctl_base + 3, 4, RF_ACTIVE);
387 		ISACTL(CtlP)->MReg0IO = 0;
388 		ISACTL(CtlP)->MReg1IO = 1;
389 		ISACTL(CtlP)->MReg2IO = 2;
390 		ISACTL(CtlP)->MReg3IO = 3;
393 	ISACTL(CtlP)->MReg2 = 0;			/* interrupt disable */
394 	ISACTL(CtlP)->MReg3 = 0;			/* no periodic interrupts */
398 		ISACTL(CtlP)->MReg2 = 0;		/* interrupt disable */
399 		ISACTL(CtlP)->MReg3 = 0;		/* no periodic interrupts */
403 		ISACTL(CtlP)->MReg2 = sIRQMap[IRQNum];	/* set IRQ number */
404 		ISACTL(CtlP)->MReg3 = Frequency;	/* set frequency */
407 			ISACTL(CtlP)->MReg3 |= PERIODIC_ONLY;
411 	rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2);
412 	rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3);
413 	sControllerEOI(MudbacCtlP,CtlP);			/* clear EOI if warm init */
416 	CtlP->NumAiop = 0;
419 		if (CtlP->io[i] == NULL) {
420 			CtlP->io_rid[i] = i;
421 			aiop_base = rman_get_start(CtlP->io[0]) + 0x400 * i;
426 			CtlP->io[i] = bus_alloc_resource(CtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[i], aiop_base, aiop_base + aiop_size - 1, aiop_size, RF_ACTIVE);
428 			aiop_base = rman_get_start(CtlP->io[i]);
429 		rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
430 			    ISACTL(CtlP)->MReg2IO,
431 			    ISACTL(CtlP)->MReg2 | (i & 0x03));	/* AIOP index */
432 		rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
433 			    ISACTL(CtlP)->MReg0IO,
435 		sEnAiop(MudbacCtlP,CtlP,i);			/* enable the AIOP */
437 		CtlP->AiopID[i] = sReadAiopID(CtlP, i);		/* read AIOP ID */
438 		if(CtlP->AiopID[i] == AIOPID_NULL)		/* if AIOP does not exist */
440 			sDisAiop(MudbacCtlP,CtlP,i);		/* disable AIOP */
441 			bus_release_resource(CtlP->dev, SYS_RES_IOPORT, CtlP->io_rid[i], CtlP->io[i]);
442 			CtlP->io[i] = NULL;
446 		CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);	/* num channels in AIOP */
447 		rp_writeaiop2(CtlP,i,_INDX_ADDR,_CLK_PRE);	/* clock prescaler */
448 		rp_writeaiop1(CtlP,i,_INDX_DATA,CLOCK_PRESC);
449 		CtlP->NumAiop++;				/* bump count of AIOPs */
450 		sDisAiop(MudbacCtlP,CtlP,i);			/* disable AIOP */
453 	if(CtlP->NumAiop == 0)
456 		return(CtlP->NumAiop);