Lines Matching defs:mh
98 pCmd = (type *)&mh->mh_cmdbuf[0]; \
127 struct mwl_hal_priv *mh; /* back pointer */
136 #define MWLVAP(_vap) ((_vap)->mh)
197 MWL_HAL_LOCK(struct mwl_hal_priv *mh)
199 mtx_lock(&mh->mh_mtx);
203 MWL_HAL_LOCK_ASSERT(struct mwl_hal_priv *mh)
205 mtx_assert(&mh->mh_mtx, MA_OWNED);
209 MWL_HAL_UNLOCK(struct mwl_hal_priv *mh)
211 mtx_unlock(&mh->mh_mtx);
215 RD4(struct mwl_hal_priv *mh, bus_size_t off)
217 return bus_space_read_4(mh->public.mh_iot, mh->public.mh_ioh, off);
221 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val)
223 bus_space_write_4(mh->public.mh_iot, mh->public.mh_ioh, off, val);
246 struct mwl_hal_priv *mh;
250 mh = malloc(sizeof(struct mwl_hal_priv), M_DEVBUF, M_NOWAIT | M_ZERO);
251 if (mh == NULL)
253 mh->mh_dev = dev;
254 mh->public.mh_ioh = ioh;
255 mh->public.mh_iot = iot;
257 mh->mh_streams[i].public.txq = ba2qid[i];
258 mh->mh_streams[i].stream = i;
260 if (mh->mh_streams[i].public.txq < MWL_BAQID_MAX)
261 qid2ba[mh->mh_streams[i].public.txq] = i;
264 "stream %d\n", mh->mh_streams[i].public.txq, i);
269 hvap = &mh->mh_vaps[i];
274 hvap = &mh->mh_vaps[i];
279 hvap = &mh->mh_vaps[i];
284 hvap = &mh->mh_vaps[i];
289 mh->mh_revs.mh_devid = devid;
290 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname),
292 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF);
310 &mh->mh_dmat);
318 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf,
320 &mh->mh_dmamap);
327 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap,
328 mh->mh_cmdbuf, MWL_CMDBUF_SIZE,
329 mwl_hal_load_cb, &mh->mh_cmdaddr,
349 mh->mh_SDRAMSIZE_Addr = 0x40fe70b7; /* 8M SDRAM */
352 mh->mh_SDRAMSIZE_Addr = 0x40fc70b7; /* 16M SDRAM */
357 return &mh->public;
359 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
361 bus_dma_tag_destroy(mh->mh_dmat);
363 mtx_destroy(&mh->mh_mtx);
364 free(mh, M_DEVBUF);
371 struct mwl_hal_priv *mh = MWLPRIV(mh0);
373 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
374 bus_dma_tag_destroy(mh->mh_dmat);
375 mtx_destroy(&mh->mh_mtx);
376 free(mh, M_DEVBUF);
383 mwlResetHalState(struct mwl_hal_priv *mh)
388 mh->mh_bastreams = (1<<MWL_BASTREAMS_MAX)-1;
390 mh->mh_vaps[i].mh = NULL;
394 mh->mh_RTSSuccesses = 0;
395 mh->mh_RTSFailures = 0;
396 mh->mh_RxDuplicateFrames = 0;
397 mh->mh_FCSErrorCount = 0;
403 if ((mh->mh_flags & MHF_CALDATA) == 0)
404 mwlGetPwrCalTable(mh);
412 struct mwl_hal_priv *mh = MWLPRIV(mh0);
416 MWL_HAL_LOCK(mh);
419 vap = &mh->mh_vaps[i];
420 if (vap->vap_type == type && vap->mh == NULL) {
421 vap->mh = mh;
426 MWL_HAL_UNLOCK(mh);
434 vap->mh = NULL;
444 mwl_hal_setdebug(struct mwl_hal *mh, int debug)
446 MWLPRIV(mh)->mh_debug = debug;
450 mwl_hal_getdebug(struct mwl_hal *mh)
452 return MWLPRIV(mh)->mh_debug;
456 mwl_hal_setbastreams(struct mwl_hal *mh, int mask)
458 MWLPRIV(mh)->mh_bastreams = mask & ((1<<MWL_BASTREAMS_MAX)-1);
462 mwl_hal_getbastreams(struct mwl_hal *mh)
464 return MWLPRIV(mh)->mh_bastreams;
468 mwl_hal_ismbsscapable(struct mwl_hal *mh)
470 return (MWLPRIV(mh)->mh_flags & MHF_MBSS) != 0;
482 struct mwl_hal_priv *mh = MWLPRIV(mh0);
485 cause = RD4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE);
487 device_printf(mh->mh_dev, "%s: cause 0x%x\n", __func__, cause);
491 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
492 cause &~ mh->public.mh_imask);
493 RD4(mh, MACREG_REG_INT_CODE); /* XXX flush write? */
505 struct mwl_hal_priv *mh = MWLPRIV(mh0);
507 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
508 RD4(mh, MACREG_REG_INT_CODE);
510 mh->public.mh_imask = mask;
511 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
512 RD4(mh, MACREG_REG_INT_CODE);
525 struct mwl_hal_priv *mh = MWLPRIV(mh0);
528 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
529 dummy = RD4(mh, MACREG_REG_INT_CODE);
542 struct mwl_hal_priv *mh = MWLPRIV(mh0);
544 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE) {
545 device_printf(mh->mh_dev, "cmd done interrupt:\n");
546 dumpresult(mh, 1);
560 struct mwl_hal_priv *mh = MWLPRIV(mh0);
564 MWL_HAL_LOCK(mh);
567 pCmd->ulFwAwakeCookie = htole32((unsigned int)mh->mh_cmdaddr+2048);
569 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_HW_SPEC);
586 mh->mh_revs.mh_macRev = hw->hwVersion; /* XXX */
587 mh->mh_revs.mh_phyRev = hw->hostInterface; /* XXX */
592 mh->mh_bastreams &= (1<<MWL_BASTREAMS_MAX)-1;
594 mh->mh_bastreams &= (1<<2)-1;
596 MWL_HAL_UNLOCK(mh);
608 struct mwl_hal_priv *mh = MWLPRIV(mh0);
612 MWL_HAL_LOCK(mh);
628 if (mh->mh_revs.mh_macRev < 5)
631 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_HW_SPEC);
634 mh->mh_flags &= ~MHF_MBSS;
636 mh->mh_flags |= MHF_MBSS;
638 MWL_HAL_UNLOCK(mh);
649 struct mwl_hal_priv *mh = MWLPRIV(mh0);
653 MWL_HAL_LOCK(mh);
657 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_GET_STAT);
671 mh->mh_RTSSuccesses += RD4(mh, 0xa834);
672 mh->mh_RTSFailures += RD4(mh, 0xa830);
673 mh->mh_RxDuplicateFrames += RD4(mh, 0xa84c);
674 mh->mh_FCSErrorCount += RD4(mh, 0xa840);
676 MWL_HAL_UNLOCK(mh);
678 stats->RTSSuccesses = mh->mh_RTSSuccesses;
679 stats->RTSFailures = mh->mh_RTSFailures;
680 stats->RxDuplicateFrames = mh->mh_RxDuplicateFrames;
681 stats->FCSErrorCount = mh->mh_FCSErrorCount;
692 struct mwl_hal_priv *mh = MWLVAP(vap);
696 MWL_HAL_LOCK(mh);
709 retval = mwlExecuteCmd(mh, HostCmd_CMD_HT_GUARD_INTERVAL);
710 MWL_HAL_UNLOCK(mh);
722 struct mwl_hal_priv *mh = MWLPRIV(mh0);
726 MWL_HAL_LOCK(mh);
736 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RADIO_CONTROL);
737 MWL_HAL_UNLOCK(mh);
750 struct mwl_hal_priv *mh = MWLPRIV(mh0);
757 MWL_HAL_LOCK(mh);
765 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_ANTENNA);
766 MWL_HAL_UNLOCK(mh);
778 struct mwl_hal_priv *mh = MWLVAP(vap);
782 MWL_HAL_LOCK(mh);
788 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RTS_THSD);
789 MWL_HAL_UNLOCK(mh);
799 struct mwl_hal_priv *mh = MWLVAP(vap);
803 MWL_HAL_LOCK(mh);
807 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_INFRA_MODE);
808 MWL_HAL_UNLOCK(mh);
818 struct mwl_hal_priv *mh = MWLPRIV(mh0);
822 MWL_HAL_LOCK(mh);
827 if (mh->mh_regioncode == DOMAIN_CODE_ETSI_131)
830 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11H_DETECT_RADAR);
831 MWL_HAL_UNLOCK(mh);
887 struct mwl_hal_priv *mh = MWLPRIV(mh0);
891 MWL_HAL_LOCK(mh);
899 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_SWITCH_CHANNEL);
900 MWL_HAL_UNLOCK(mh);
910 struct mwl_hal_priv *mh = MWLPRIV(mh0);
914 MWL_HAL_LOCK(mh);
927 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_REGION_CODE);
929 mh->mh_regioncode = regionCode;
930 MWL_HAL_UNLOCK(mh);
941 struct mwl_hal_priv *mh = MWLVAP(vap);
946 MWL_HAL_LOCK(mh);
986 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
987 MWL_HAL_UNLOCK(mh);
994 struct mwl_hal_priv *mh = MWLPRIV(mh0);
998 MWL_HAL_LOCK(mh);
1009 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
1010 MWL_HAL_UNLOCK(mh);
1020 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1027 MWL_HAL_LOCK(mh);
1033 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_SET_SLOT);
1034 MWL_HAL_UNLOCK(mh);
1041 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1045 MWL_HAL_LOCK(mh);
1058 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1059 MWL_HAL_UNLOCK(mh);
1064 findchannel(const struct mwl_hal_priv *mh, const MWL_HAL_CHANNEL *c)
1073 ci = &mh->mh_40M;
1077 ci = &mh->mh_20M;
1082 ci = &mh->mh_40M_5G;
1086 ci = &mh->mh_20M_5G;
1100 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1105 hc = findchannel(mh, c);
1108 device_printf(mh->mh_dev,
1115 MWL_HAL_LOCK(mh);
1129 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1130 MWL_HAL_UNLOCK(mh);
1138 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1142 *ci = (chw == MWL_CH_20_MHz_WIDTH) ? &mh->mh_20M : &mh->mh_40M;
1146 &mh->mh_20M_5G : &mh->mh_40M_5G;
1157 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1164 MWL_HAL_LOCK(mh);
1171 retval = mwlExecuteCmd(mh, HostCmd_CMD_MAC_MULTICAST_ADR);
1172 MWL_HAL_UNLOCK(mh);
1180 struct mwl_hal_priv *mh = MWLVAP(vap);
1184 MWL_HAL_LOCK(mh);
1221 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1222 MWL_HAL_UNLOCK(mh);
1229 struct mwl_hal_priv *mh = MWLVAP(vap);
1233 MWL_HAL_LOCK(mh);
1246 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1247 MWL_HAL_UNLOCK(mh);
1255 struct mwl_hal_priv *mh = MWLVAP(vap);
1264 return mwlExecuteCmd(mh, HostCmd_CMD_SET_MAC_ADDR);
1270 struct mwl_hal_priv *mh = MWLVAP(vap);
1273 MWL_HAL_LOCK(mh);
1275 MWL_HAL_UNLOCK(mh);
1282 struct mwl_hal_priv *mh = MWLVAP(vap);
1287 MWL_HAL_LOCK(mh);
1294 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_BEACON);
1295 MWL_HAL_UNLOCK(mh);
1302 struct mwl_hal_priv *mh = MWLVAP(vap);
1306 MWL_HAL_LOCK(mh);
1311 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_POWERSAVESTATION);
1312 MWL_HAL_UNLOCK(mh);
1319 struct mwl_hal_priv *mh = MWLVAP(vap);
1323 MWL_HAL_LOCK(mh);
1328 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_TIM);
1329 MWL_HAL_UNLOCK(mh);
1337 struct mwl_hal_priv *mh = MWLVAP(vap);
1338 HostCmd_FW_SET_AID *pCmd = (HostCmd_FW_SET_AID *) &mh->mh_cmdbuf[0];
1341 MWL_HAL_LOCK(mh);
1346 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_AID);
1347 MWL_HAL_UNLOCK(mh);
1354 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1358 MWL_HAL_LOCK(mh);
1364 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RF_CHANNEL);
1365 MWL_HAL_UNLOCK(mh);
1374 struct mwl_hal_priv *mh = MWLVAP(vap);
1378 MWL_HAL_LOCK_ASSERT(mh);
1399 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1417 struct mwl_hal_priv *mh = MWLVAP(vap);
1421 MWL_HAL_LOCK(mh);
1422 if (mh->mh_bastreams == 0) {
1424 MWL_HAL_UNLOCK(mh);
1427 for (s = 0; (mh->mh_bastreams & (1<<s)) == 0; s++)
1430 MWL_HAL_UNLOCK(mh);
1433 sp = &mh->mh_streams[s];
1434 mh->mh_bastreams &= ~(1<<s);
1442 MWL_HAL_UNLOCK(mh);
1449 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1453 if (mh->mh_bastreams & (1<<s))
1455 return &mh->mh_streams[s].public;
1466 struct mwl_hal_priv *mh = MWLVAP(vap);
1471 MWL_HAL_LOCK(mh);
1500 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1512 MWL_HAL_UNLOCK(mh);
1519 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1528 MWL_HAL_LOCK(mh);
1535 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1539 mh->mh_bastreams |= 1<<sp->stream;
1543 MWL_HAL_UNLOCK(mh);
1552 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1557 MWL_HAL_LOCK(mh);
1562 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_SEQNO);
1565 MWL_HAL_UNLOCK(mh);
1572 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1576 MWL_HAL_LOCK(mh);
1580 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_WATCHDOG_BITMAP);
1587 MWL_HAL_UNLOCK(mh);
1597 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1601 MWL_HAL_LOCK(mh);
1608 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1609 MWL_HAL_UNLOCK(mh);
1616 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1620 MWL_HAL_LOCK(mh);
1625 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1626 MWL_HAL_UNLOCK(mh);
1638 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1642 MWL_HAL_LOCK(mh);
1647 retval = mwlExecuteCmd(mh, HostCmd_CMD_CFEND_ENABLE);
1648 MWL_HAL_UNLOCK(mh);
1656 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1659 MWL_HAL_LOCK(mh);
1662 retval = mwlExecuteCmd(mh, HostCmd_CMD_DWDS_ENABLE);
1663 MWL_HAL_UNLOCK(mh);
1687 struct mwl_hal_priv *mh = MWLVAP(vap);
1691 MWL_HAL_LOCK(mh);
1704 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1707 MWL_HAL_UNLOCK(mh);
1715 struct mwl_hal_priv *mh = MWLVAP(vap);
1719 MWL_HAL_LOCK(mh);
1726 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1731 MWL_HAL_UNLOCK(mh);
1742 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1746 MWL_HAL_LOCK(mh);
1755 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_KEEP_ALIVE);
1756 MWL_HAL_UNLOCK(mh);
1763 struct mwl_hal_priv *mh = MWLVAP(vap);
1769 MWL_HAL_LOCK(mh);
1773 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_APMODE);
1774 MWL_HAL_UNLOCK(mh);
1781 struct mwl_hal_priv *mh = MWLVAP(vap);
1785 MWL_HAL_LOCK(mh);
1790 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1795 MWL_HAL_UNLOCK(mh);
1802 struct mwl_hal_priv *mh = MWLVAP(vap);
1806 MWL_HAL_LOCK(mh);
1810 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1813 MWL_HAL_UNLOCK(mh);
1820 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1824 MWL_HAL_LOCK(mh);
1829 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_G_PROTECT_FLAG);
1830 MWL_HAL_UNLOCK(mh);
1837 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1841 MWL_HAL_LOCK(mh);
1846 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_WMM_MODE);
1847 MWL_HAL_UNLOCK(mh);
1855 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1859 MWL_HAL_LOCK(mh);
1874 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_EDCA_PARAMS);
1875 MWL_HAL_UNLOCK(mh);
1883 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1887 MWL_HAL_LOCK(mh);
1893 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RATE_ADAPT_MODE);
1894 MWL_HAL_UNLOCK(mh);
1901 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1905 MWL_HAL_LOCK(mh);
1911 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1912 MWL_HAL_UNLOCK(mh);
1919 struct mwl_hal_priv *mh = MWLVAP(vap);
1924 MWL_HAL_LOCK(mh);
1929 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_FLAG);
1930 MWL_HAL_UNLOCK(mh);
1937 struct mwl_hal_priv *mh = MWLVAP(vap);
1941 MWL_HAL_LOCK(mh);
1946 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_OPMODE);
1947 MWL_HAL_UNLOCK(mh);
1954 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1958 MWL_HAL_LOCK(mh);
1963 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1964 MWL_HAL_UNLOCK(mh);
1972 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1976 MWL_HAL_LOCK(mh);
1982 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_MIMOPSHT);
1983 MWL_HAL_UNLOCK(mh);
1988 mwlGetCalTable(struct mwl_hal_priv *mh, uint8_t annex, uint8_t index)
1993 MWL_HAL_LOCK_ASSERT(mh);
2000 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_CALTABLE);
2097 mwlGetPwrCalTable(struct mwl_hal_priv *mh)
2103 MWL_HAL_LOCK(mh);
2105 data = ((const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf)->calTbl;
2106 if (mwlGetCalTable(mh, 33, 0) == 0) {
2113 get2Ghz(&mh->mh_20M, &data[12], len);
2115 if (mwlGetCalTable(mh, 34, 0) == 0) {
2122 ci = &mh->mh_40M;
2125 if (mwlGetCalTable(mh, 35, 0) == 0) {
2132 get5Ghz(&mh->mh_20M_5G, &data[20], len);
2134 if (mwlGetCalTable(mh, 36, 0) == 0) {
2141 ci = &mh->mh_40M_5G;
2144 mh->mh_flags |= MHF_CALDATA;
2145 MWL_HAL_UNLOCK(mh);
2152 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2155 MWL_HAL_LOCK(mh);
2156 retval = mwlGetCalTable(mh, 0, 0);
2159 (const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf;
2162 MWL_HAL_UNLOCK(mh);
2169 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2172 MWL_HAL_LOCK(mh);
2173 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2174 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2175 MWL_HAL_UNLOCK(mh);
2182 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2185 MWL_HAL_LOCK(mh);
2186 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2187 MWL_HAL_UNLOCK(mh);
2194 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2198 MWL_HAL_LOCK(mh);
2202 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_BEACON);
2208 MWL_HAL_UNLOCK(mh);
2215 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2219 MWL_HAL_LOCK(mh);
2223 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RIFS);
2224 MWL_HAL_UNLOCK(mh);
2233 getRFReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2238 MWL_HAL_LOCK(mh);
2244 retval = mwlExecuteCmd(mh, HostCmd_CMD_RF_REG_ACCESS);
2247 MWL_HAL_UNLOCK(mh);
2252 getBBReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2257 MWL_HAL_LOCK(mh);
2263 retval = mwlExecuteCmd(mh, HostCmd_CMD_BBP_REG_ACCESS);
2266 MWL_HAL_UNLOCK(mh);
2271 mwl_hal_getregdump(struct mwl_hal_priv *mh, const MWL_DIAG_REGRANGE *regs,
2284 *dp = RD4(mh, r);
2286 getBBReg(mh, HostCmd_ACT_GEN_READ,
2289 getRFReg(mh, HostCmd_ACT_GEN_READ,
2292 *dp = RD4(mh, r);
2308 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2312 *result = &mh->mh_revs;
2313 *resultsize = sizeof(mh->mh_revs);
2316 *resultsize = mwl_hal_getregdump(mh, args, *result, *resultsize);
2319 FWCmdHdr *pCmd = (FWCmdHdr *) &mh->mh_cmdbuf[0];
2322 MWL_HAL_LOCK(mh);
2324 retval = mwlExecuteCmd(mh, le16toh(pCmd->Cmd));
2326 MWL_HAL_UNLOCK(mh);
2331 device_printf(mh->mh_dev, "problem loading fw image\n");
2344 mwlSendCmd(struct mwl_hal_priv *mh)
2348 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2351 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2352 dummy = RD4(mh, MACREG_REG_INT_CODE);
2354 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2358 mwlWaitForCmdComplete(struct mwl_hal_priv *mh, uint16_t cmdCode)
2364 if (mh->mh_cmdbuf[0] == le16toh(cmdCode))
2373 mwlExecuteCmd(struct mwl_hal_priv *mh, unsigned short cmd)
2376 MWL_HAL_LOCK_ASSERT(mh);
2378 if ((mh->mh_flags & MHF_FWHANG) &&
2379 (mh->mh_debug & MWL_HAL_DEBUG_IGNHANG) == 0) {
2381 device_printf(mh->mh_dev, "firmware hung, skipping cmd %s\n",
2384 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n",
2389 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2390 device_printf(mh->mh_dev, "%s: device not present!\n",
2395 if (mh->mh_debug & MWL_HAL_DEBUG_SENDCMD)
2396 dumpresult(mh, 0);
2398 mwlSendCmd(mh);
2399 if (!mwlWaitForCmdComplete(mh, 0x8000 | cmd)) {
2401 device_printf(mh->mh_dev,
2404 device_printf(mh->mh_dev,
2407 mh->mh_flags |= MHF_FWHANG;
2410 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2413 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE)
2414 dumpresult(mh, 1);
2433 mwlFwReset(struct mwl_hal_priv *mh)
2435 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2436 device_printf(mh->mh_dev, "%s: device not present!\n",
2440 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2441 mh->mh_flags &= ~MHF_FWHANG;
2445 mwlTriggerPciCmd(struct mwl_hal_priv *mh)
2449 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE);
2451 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2452 dummy = RD4(mh, MACREG_REG_INT_CODE);
2454 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2455 dummy = RD4(mh, MACREG_REG_INT_CODE);
2457 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2458 dummy = RD4(mh, MACREG_REG_INT_CODE);
2462 mwlWaitFor(struct mwl_hal_priv *mh, uint32_t val)
2468 if (RD4(mh, MACREG_REG_INT_CODE) == val)
2478 mwlSendBlock(struct mwl_hal_priv *mh, int bsize, const void *data, size_t dsize)
2480 mh->mh_cmdbuf[0] = htole16(HostCmd_CMD_CODE_DNLD);
2481 mh->mh_cmdbuf[1] = htole16(bsize);
2482 memcpy(&mh->mh_cmdbuf[4], data , dsize);
2483 mwlTriggerPciCmd(mh);
2485 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2486 WR4(mh, MACREG_REG_INT_CODE, 0);
2489 device_printf(mh->mh_dev,
2491 __func__, RD4(mh, MACREG_REG_INT_CODE));
2499 mwlSendBlock2(struct mwl_hal_priv *mh, const void *data, size_t dsize)
2501 memcpy(&mh->mh_cmdbuf[0], data, dsize);
2502 mwlTriggerPciCmd(mh);
2503 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2504 WR4(mh, MACREG_REG_INT_CODE, 0);
2507 device_printf(mh->mh_dev,
2509 __func__, RD4(mh, MACREG_REG_INT_CODE));
2514 mwlPokeSdramController(struct mwl_hal_priv *mh, int SDRAMSIZE_Addr)
2517 WR4(mh, 0x00006014, 0x33);
2518 WR4(mh, 0x00006018, 0xa3a2632);
2519 WR4(mh, 0x00006010, SDRAMSIZE_Addr);
2525 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2540 device_printf(mh->mh_dev,
2547 device_printf(mh->mh_dev, "firmware image %s too small\n",
2559 device_printf(mh->mh_dev,
2567 mwlFwReset(mh);
2569 WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
2570 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
2571 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
2572 WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
2573 if (mh->mh_SDRAMSIZE_Addr != 0) {
2575 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2577 device_printf(mh->mh_dev, "load %s firmware image (%u bytes)\n",
2590 if (!mwlSendBlock(mh, fwboot->datasize, fwboot->data, fwboot->datasize) ||
2591 !mwlSendBlock(mh, 0, NULL, 0)) {
2596 if (mh->mh_SDRAMSIZE_Addr != 0) {
2598 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2602 WR4(mh, MACREG_REG_INT_CODE, 0);
2603 blocksize = RD4(mh, MACREG_REG_SCRATCH);
2631 if (!mwlSendBlock2(mh, fp, nbytes)) {
2641 if (!mwlSendBlock(mh, FW_DOWNLOAD_BLOCK_SIZE, fp, nbytes)) {
2657 mh->mh_cmdbuf[1] = 0;
2662 mwlTriggerPciCmd(mh);
2664 WR4(mh, MACREG_REG_GEN_PTR, OpMode);
2666 if (RD4(mh, MACREG_REG_INT_CODE) == FwReadySignature) {
2667 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2668 return mwlResetHalState(mh);
2673 mwlFwReset(mh);
2744 dumpresult(struct mwl_hal_priv *mh, int showresult)
2746 const FWCmdHdr *h = (const FWCmdHdr *)mh->mh_cmdbuf;
2752 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d MacId %d",
2755 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d",