Lines Matching defs:WR4
221 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val)
491 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
507 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
511 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
528 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
2174 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2351 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2354 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2440 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2451 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2454 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2457 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2486 WR4(mh, MACREG_REG_INT_CODE, 0);
2504 WR4(mh, MACREG_REG_INT_CODE, 0);
2517 WR4(mh, 0x00006014, 0x33);
2518 WR4(mh, 0x00006018, 0xa3a2632);
2519 WR4(mh, 0x00006010, SDRAMSIZE_Addr);
2569 WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
2570 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
2571 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
2572 WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
2602 WR4(mh, MACREG_REG_INT_CODE, 0);
2664 WR4(mh, MACREG_REG_GEN_PTR, OpMode);
2667 WR4(mh, MACREG_REG_INT_CODE, 0x00);