Lines Matching refs:BIT_0
190 #define BIT_0 (1 << 0)
307 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
339 #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
372 #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
389 #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
402 #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */
802 #define CS_RST_SET BIT_0 /* Set Software Reset */
805 #define LED_STAT_OFF BIT_0 /* Status LED Off */
815 #define PC_VCC_OFF BIT_0 /* Switch VCC Off */
845 #define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
878 #define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
892 #define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
939 #define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */
944 #define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */
962 #define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */
968 #define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */
975 #define TIM_T_STEP BIT_0 /* Test step */
983 #define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */
993 #define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */
1021 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
1024 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
1029 #define I2C_CLK BIT_0 /* I2C Clock Port */
1037 #define BSC_STOP BIT_0 /* Stop Blink Source Counter */
1040 #define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */
1045 #define BSC_T_STEP BIT_0 /* Test step */
1059 #define RI_RST_SET BIT_0 /* Set RAM Interface Reset */
1078 #define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */
1086 #define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */
1089 #define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */
1114 #define BMU_RST_SET BIT_0 /* Set BMU Reset */
1144 #define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
1163 #define RB_PC_INC BIT_0 /* Packet Counter Increment */
1171 #define RB_RP_INC BIT_0 /* Read Pointer Increment */
1179 #define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */
1236 #define WOL_CTL_DIS_PATTERN_UNIT BIT_0
1247 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
1387 #define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */
1435 #define PHY_M_PS_JABBER BIT_0 /* Jabber */
1459 #define PHY_M_IS_JABBER BIT_0 /* Jabber */
1481 #define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */
1511 #define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */
1512 #define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */
1612 #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
1838 #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
1920 #define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
1979 #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
2006 #define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */
2014 #define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
2022 #define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */
2044 #define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0
2047 #define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0
2052 #define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
2059 #define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
2077 #define GMC_RST_SET BIT_0 /* Set GMAC Reset */
2102 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
2111 #define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
2117 #define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */