Lines Matching refs:jme_phyaddr
770 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
774 sc->jme_phyaddr);
776 sc->jme_phyaddr = 0;
843 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr,
858 sc->jme_phyaddr = miisc->mii_phy;
862 if (sc->jme_phyaddr != 0) {
864 "FPGA PHY is at %d\n", sc->jme_phyaddr);
866 jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
1543 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1544 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1546 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
2180 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2184 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2921 reg |= sc->jme_phyaddr;
3373 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN);
3391 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR);
3393 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr);