Lines Matching refs:u16
88 u16 oem_build = (u16)((hw->nvm.oem_ver >> 16) & 0xFFFF);
290 u16 needed;
1307 u16 pci_cmd_word;
1493 u16 vector = 1;
1914 u16 next = 0;
2034 u16 size;
2075 u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len;
2340 u16 rx_itr;
2341 u16 rx_latency = 0;
2414 u16 tx_itr;
2415 u16 tx_latency = 0;
2944 ixl_register_vlan(void *arg, struct ifnet *ifp, u16 vtag)
2968 ixl_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag)
3295 ixl_enable_tx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
3300 u16 pf_qidx;
3331 ixl_enable_rx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
3336 u16 pf_qidx;
3365 ixl_enable_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
3394 ixl_disable_tx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
3399 u16 pf_qidx;
3426 ixl_disable_rx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
3431 u16 pf_qidx;
3455 ixl_disable_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
3505 u16 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
3520 u16 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
3920 u16 opcode, result;
3988 u16 stat_idx = vsi->info.stat_counter_idx;
4525 u16 link;
5406 u16 next = 0;