dev/ixl/i40e_common.c

1440  * Make sure all PXE mode settings are cleared, including things
1716 	/* clear the old pause settings */
1723 		/* Auto restart link so settings take effect */
1726 		/* Copy over all the old settings */
1761  * Configure MAC settings for frame size, jumbo frame support and the
4749  * EMP will return when the shared RPB settings have been
5135  * @settings: Filter control settings
5137  * Check and validate the filter control settings passed.
5145 				struct i40e_filter_control_settings *settings)
5153 	/* Validate FCoE settings passed */
5154 	switch (settings->fcoe_filt_num) {
5162 		fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5168 	switch (settings->fcoe_cntx_num) {
5174 		fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5180 	/* Validate PE settings passed */
5181 	switch (settings->pe_filt_num) {
5194 		pe_filt_size <<= (u32)settings->pe_filt_num;
5200 	switch (settings->pe_cntx_num) {
5212 		pe_cntx_size <<= (u32)settings->pe_cntx_num;
5231  * @settings: Filter control settings
5234  * for a single PF. It is expected that these settings are programmed
5238 				struct i40e_filter_control_settings *settings)
5244 	if (!settings)
5247 	/* Validate the input settings */
5248 	ret = i40e_validate_filter_settings(hw, settings);
5257 	val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5261 	val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5266 	val |= ((u32)settings->fcoe_filt_num <<
5271 	val |= ((u32)settings->fcoe_cntx_num <<
5277 	if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5283 	if (settings->enable_fdir)
5285 	if (settings->enable_ethtype)
5287 	if (settings->enable_macvlan)