dev/ixl/i40e_adminq.c

51 		hw->aq.asq.tail = I40E_VF_ATQT1;
52 		hw->aq.asq.head = I40E_VF_ATQH1;
53 		hw->aq.asq.len  = I40E_VF_ATQLEN1;
54 		hw->aq.asq.bal  = I40E_VF_ATQBAL1;
55 		hw->aq.asq.bah  = I40E_VF_ATQBAH1;
62 		hw->aq.asq.tail = I40E_PF_ATQT;
63 		hw->aq.asq.head = I40E_PF_ATQH;
64 		hw->aq.asq.len  = I40E_PF_ATQLEN;
65 		hw->aq.asq.bal  = I40E_PF_ATQBAL;
66 		hw->aq.asq.bah  = I40E_PF_ATQBAH;
83 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
91 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
95 		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
128 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
221 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
225 	hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
229 		bi = &hw->aq.asq.r.asq_bi[i];
244 		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
245 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
279 		if (hw->aq.asq.r.asq_bi[i].pa)
280 			i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
283 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
286 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
289 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
304 	wr32(hw, hw->aq.asq.head, 0);
305 	wr32(hw, hw->aq.asq.tail, 0);
309 		wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
312 		wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
314 	wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
315 	wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
318 	reg = rd32(hw, hw->aq.asq.bal);
319 	if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
378 	if (hw->aq.asq.count > 0) {
391 	hw->aq.asq.next_to_use = 0;
392 	hw->aq.asq.next_to_clean = 0;
410 	hw->aq.asq.count = hw->aq.num_asq_entries;
491 	if (hw->aq.asq.count == 0) {
497 	wr32(hw, hw->aq.asq.head, 0);
498 	wr32(hw, hw->aq.asq.tail, 0);
499 	wr32(hw, hw->aq.asq.len, 0);
500 	wr32(hw, hw->aq.asq.bal, 0);
501 	wr32(hw, hw->aq.asq.bah, 0);
503 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */
554 	hw->aq.asq.next_to_use = 0;
555 	hw->aq.asq.next_to_clean = 0;
704 	struct i40e_adminq_ring *asq = &(hw->aq.asq);
706 	u16 ntc = asq->next_to_clean;
710 	desc = I40E_ADMINQ_DESC(*asq, ntc);
711 	details = I40E_ADMINQ_DETAILS(*asq, ntc);
712 	while (rd32(hw, hw->aq.asq.head) != ntc) {
714 			   "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
726 		if (ntc == asq->count)
728 		desc = I40E_ADMINQ_DESC(*asq, ntc);
729 		details = I40E_ADMINQ_DETAILS(*asq, ntc);
732 	asq->next_to_clean = ntc;
734 	return I40E_DESC_UNUSED(asq);
749 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
782 	if (hw->aq.asq.count == 0) {
789 	val = rd32(hw, hw->aq.asq.head);
797 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
857 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
865 		dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
884 	(hw->aq.asq.next_to_use)++;
885 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)
886 		hw->aq.asq.next_to_use = 0;
888 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);