Lines Matching refs:x7
1325 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1326 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1327 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1328 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1329 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1330 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1331 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1332 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1335 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
1430 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1515 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */
1524 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
2046 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2047 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2053 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2295 #define IXGBE_FW_PATCH_VERSION_4 0x7
2305 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */
2320 #define IXGBE_X540_FW_PATCH_VERSION_4 0x7
3273 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
3967 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
4008 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7