Lines Matching refs:CSR_WRITE_4
242 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr);
249 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr);
1239 CSR_WRITE_4(sc, data->reg, data->physaddr);
1595 CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw);
1662 CSR_WRITE_4(sc, IWI_CSR_INTR, r);
1736 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur);
1918 CSR_WRITE_4(sc, txq->csr_widx, txq->cur);
2075 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0);
2077 CSR_WRITE_4(sc, IWI_CSR_RST, IWI_RST_STOP_MASTER);
2087 CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_PRINCETON_RESET);
2101 CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
2103 CSR_WRITE_4(sc, IWI_CSR_READ_INT, IWI_READ_INT_INIT_HOST);
2118 CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_SOFT_RESET);
2123 CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
2126 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_ADDR, 0);
2128 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, 0);
2339 CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) |
2357 CSR_WRITE_4(sc, IWI_CSR_RST, tmp);
2429 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_ADDR, 0x27000);
2443 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, ctl);
2444 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, src);
2445 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, dst);
2446 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, sum);
2456 CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, 0);
2460 CSR_WRITE_4(sc, IWI_CSR_RST, tmp);
2484 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, IWI_INTR_MASK);
2487 CSR_WRITE_4(sc, IWI_CSR_RST, 0);
2490 CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_ALLOW_STANDBY);
3108 CSR_WRITE_4(sc, IWI_CSR_CMD_BASE, sc->cmdq.physaddr);
3109 CSR_WRITE_4(sc, IWI_CSR_CMD_SIZE, sc->cmdq.count);
3110 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur);
3112 CSR_WRITE_4(sc, IWI_CSR_TX1_BASE, sc->txq[0].physaddr);
3113 CSR_WRITE_4(sc, IWI_CSR_TX1_SIZE, sc->txq[0].count);
3114 CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq[0].cur);
3116 CSR_WRITE_4(sc, IWI_CSR_TX2_BASE, sc->txq[1].physaddr);
3117 CSR_WRITE_4(sc, IWI_CSR_TX2_SIZE, sc->txq[1].count);
3118 CSR_WRITE_4(sc, IWI_CSR_TX2_WIDX, sc->txq[1].cur);
3120 CSR_WRITE_4(sc, IWI_CSR_TX3_BASE, sc->txq[2].physaddr);
3121 CSR_WRITE_4(sc, IWI_CSR_TX3_SIZE, sc->txq[2].count);
3122 CSR_WRITE_4(sc, IWI_CSR_TX3_WIDX, sc->txq[2].cur);
3124 CSR_WRITE_4(sc, IWI_CSR_TX4_BASE, sc->txq[3].physaddr);
3125 CSR_WRITE_4(sc, IWI_CSR_TX4_SIZE, sc->txq[3].count);
3126 CSR_WRITE_4(sc, IWI_CSR_TX4_WIDX, sc->txq[3].cur);
3130 CSR_WRITE_4(sc, data->reg, data->physaddr);
3133 CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, sc->rxq.count - 1);
3191 CSR_WRITE_4(sc, IWI_CSR_RST, IWI_RST_SOFT_RESET);