dev/ipw/if_ipw.c

1295 	CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
1388 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1391 	CSR_WRITE_4(sc, IPW_CSR_INTR, r);
1408 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1532 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1687 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1802 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1804 	CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER);
1814 	CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET);
1830 	CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT);
1842 	CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET);
1847 	CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT);
1915 	CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1979 	CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK |
1983 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1986 	CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1989 	CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY);
1999 	CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK |
2357 	CSR_WRITE_4(sc, IPW_CSR_TX_BASE,  sc->tbd_phys);
2358 	CSR_WRITE_4(sc, IPW_CSR_TX_SIZE,  IPW_NTBD);
2359 	CSR_WRITE_4(sc, IPW_CSR_TX_READ,  0);
2360 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
2362 	CSR_WRITE_4(sc, IPW_CSR_RX_BASE,  sc->rbd_phys);
2363 	CSR_WRITE_4(sc, IPW_CSR_RX_SIZE,  IPW_NRBD);
2364 	CSR_WRITE_4(sc, IPW_CSR_RX_READ,  0);
2365 	CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
2367 	CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys);
2511 	CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET);
2534 	CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base);
2599 		CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
2610 		CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);