dev/hptrr/him.h

53 	HPT_U8  rev;
54 	HPT_U8  nbase;
61 	HPT_U8 tree;
62 	HPT_U8 bus;
63 	HPT_U8 device;
64 	HPT_U8 function;
73 	HPT_U8  max_devices;
74 	HPT_U8  reserve1;
76 	HPT_U8  bDevsPerBus;
77 	HPT_U8  first_on_slot;
79 	HPT_U8  bChipType;
80 	HPT_U8  bChipIntrNum;
81 	HPT_U8  bChipFlags;
82 	HPT_U8  bNumBuses;
84 	HPT_U8  szVendorID[36];
85 	HPT_U8  szProductID[36];
132 	HPT_U8  MaximumBlockTransfer;
133 	HPT_U8  VendorUnique2;
137 	HPT_U8  VendorUnique3;
138 	HPT_U8  PioCycleTimingMode;
139 	HPT_U8  VendorUnique4;
140 	HPT_U8  DmaCycleTimingMode;
148 	HPT_U8  SingleWordDMASupport;
149 	HPT_U8  SingleWordDMAActive;
150 	HPT_U8  MultiWordDMASupport;
151 	HPT_U8  MultiWordDMAActive;
152 	HPT_U8  AdvancedPIOModes;
153 	HPT_U8  Reserved4;
176 	HPT_U8  path_id;
177 	HPT_U8  target_id;
178 	HPT_U8  max_queue_depth;
179 	HPT_U8  spin_up_mode;
181 	HPT_U8  reserved;
182 	HPT_U8  transfer_mode;
183 	HPT_U8  bMaxShowMode;
184 	HPT_U8  bDeUsable_Mode;
210 	HPT_U8 enable;
211 	HPT_U8 depth;
215 	HPT_U8 enable;
216 	HPT_U8 depth;
220 	HPT_U8 type;
222 		HPT_U8 mode;
223 		HPT_U8 enable_read_ahead;
224 		HPT_U8 enable_read_cache;
225 		HPT_U8 enable_write_cache;
229 		HPT_U8 spin_up_mode;
230 		HPT_U8 idle_standby_timeout;
231 		HPT_U8 identify_indicator;
259 		HPT_U8 FAR * _logical;
293 	HPT_U8     bDriveHeadReg;
294 	HPT_U8     bCommandReg;
295 	HPT_U8     nSectors;
296 	HPT_U8    *pDataBuffer;
301 	HPT_U8  cdbLength;
302 	HPT_U8  senseLength;
303 	HPT_U8  scsiStatus;
304 	HPT_U8  reserve1;
306 	HPT_U8 *cdb;
307 	HPT_U8 *senseBuffer;
320 	HPT_U8  Command;
321 	HPT_U8  reserve1;
327 	HPT_U8 * logical;
343 	HPT_U8  Command;      /* CTRL_CMD_XXX */
344 	HPT_U8  reserve1;
395 	HPT_U8 type; /* CMD_TYPE_* */
398 		HPT_U8  physical_sg: 1;
399 		HPT_U8  data_in: 1;
400 		HPT_U8  data_out: 1;
401 		HPT_U8  transform : 1;
402 		HPT_U8  hard_flush: 2;
403 		HPT_U8  from_cc: 1;
404 		HPT_U8  force_cc: 1;
408 	HPT_U8  Result;
410 	HPT_U8  RetryCount;