Lines Matching refs:HPT_U8
379 HPT_U8 MaximumControllers; /* maximum controllers the driver can support */
380 HPT_U8 SupportCrossControllerRAID; /* 1-support, 0-not support */
381 HPT_U8 MinimumBlockSizeShift; /* minimum block size shift */
382 HPT_U8 MaximumBlockSizeShift; /* maximum block size shift */
384 HPT_U8 SupportDiskModeSetting;
385 HPT_U8 SupportSparePool;
386 HPT_U8 MaximumArrayNameLength;
387 /* only one HPT_U8 left here! */
389 HPT_U8 reserved: 2;
390 HPT_U8 SupportPerformanceMonitor: 1;
391 HPT_U8 SupportVariableSectorSize: 1;
392 HPT_U8 SupportHotSwap: 1;
393 HPT_U8 HighPerformanceRAID1: 1;
394 HPT_U8 RebuildProcessInDriver: 1;
395 HPT_U8 SupportDedicatedSpare: 1;
397 HPT_U8 SupportDedicatedSpare: 1; /* call hpt_add_dedicated_spare() for dedicated spare. */
398 HPT_U8 RebuildProcessInDriver: 1; /* Windows only. used by mid layer for rebuild control. */
399 HPT_U8 HighPerformanceRAID1: 1;
400 HPT_U8 SupportHotSwap: 1;
401 HPT_U8 SupportVariableSectorSize: 1;
402 HPT_U8 SupportPerformanceMonitor: 1;
403 HPT_U8 reserved: 2;
407 HPT_U8 SupportedRAIDTypes[16];
409 HPT_U8 MaximumArrayMembers[16];
415 HPT_U8 SupportedCachePolicies[16];
427 HPT_U8 ChipType; /* chip type */
428 HPT_U8 InterruptLevel; /* IRQ level */
429 HPT_U8 NumBuses; /* bus count */
430 HPT_U8 ChipFlags;
432 HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
433 HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
439 HPT_U8 ChipType; /* chip type */
440 HPT_U8 InterruptLevel; /* IRQ level */
441 HPT_U8 NumBuses; /* bus count */
442 HPT_U8 ChipFlags;
444 HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
445 HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
449 HPT_U8 pci_tree;
450 HPT_U8 pci_bus;
451 HPT_U8 pci_device;
452 HPT_U8 pci_function;
458 HPT_U8 MaxWidth;
459 HPT_U8 CurrentWidth;
460 HPT_U8 MaxSpeed;
461 HPT_U8 CurrentSpeed;
462 HPT_U8 reserve[64];
494 HPT_U8 ChipType;
495 HPT_U8 InterruptLevel;
496 HPT_U8 NumBuses;
497 HPT_U8 ChipFlags;
498 HPT_U8 szProductID[MAX_NAME_LENGTH];
499 HPT_U8 szVendorID[MAX_NAME_LENGTH];
501 HPT_U8 pci_tree;
502 HPT_U8 pci_bus;
503 HPT_U8 pci_device;
504 HPT_U8 pci_function;
506 HPT_U8 IOPModel[32];
508 HPT_U8 BatteryInstalled;
509 HPT_U8 BatteryStatus;
513 HPT_U8 SerialNumber[32];
514 HPT_U8 BatteryMBInstalled;
515 HPT_U8 BatteryTemperature;
532 HPT_U8 SASAddress[8];
533 HPT_U8 reserve[48];
557 HPT_U8 EnclosureType;
558 HPT_U8 NumberOfPhys;
559 HPT_U8 AttachedTo;
560 HPT_U8 Status;
561 HPT_U8 VendorId[8];
562 HPT_U8 ProductId[16];
563 HPT_U8 ProductRevisionLevel[4];
570 HPT_U8 ElementType;
571 HPT_U8 ElementOverallIndex;
572 HPT_U8 ElementStatus;
573 HPT_U8 Reserved;
575 HPT_U8 ElementDescriptor[32];
619 HPT_U8 EnclosureType;
620 HPT_U8 NumberOfPhys;
621 HPT_U8 AttachedTo;
622 HPT_U8 Status;
623 HPT_U8 VendorId[8];
624 HPT_U8 ProductId[16];
625 HPT_U8 ProductRevisionLevel[4];
631 HPT_U8 EnclosureType;
632 HPT_U8 NumberOfPhys;
633 HPT_U8 AttachedTo;
634 HPT_U8 Status;
635 HPT_U8 VendorId[8];
636 HPT_U8 ProductId[16];
637 HPT_U8 ProductRevisionLevel[4];
645 HPT_U8 EnclosureType;
646 HPT_U8 NumberOfPhys;
647 HPT_U8 AttachedTo;
648 HPT_U8 Status;
649 HPT_U8 VendorId[8];
650 HPT_U8 ProductId[16];
651 HPT_U8 ProductRevisionLevel[4];
682 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
683 HPT_U8 Description[64]; /* array description */
684 HPT_U8 CreateManager[16]; /* who created it */
687 HPT_U8 ArrayType; /* array type */
688 HPT_U8 BlockSizeShift; /* stripe size */
689 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
690 HPT_U8 SubArrayType;
709 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
710 HPT_U8 Description[64]; /* array description */
711 HPT_U8 CreateManager[16]; /* who created it */
714 HPT_U8 ArrayType; /* array type */
715 HPT_U8 BlockSizeShift; /* stripe size */
716 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
717 HPT_U8 SubArrayType;
731 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
732 HPT_U8 Description[64]; /* array description */
733 HPT_U8 CreateManager[16]; /* who created it */
736 HPT_U8 ArrayType; /* array type */
737 HPT_U8 BlockSizeShift; /* stripe size */
738 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
739 HPT_U8 SubArrayType;
764 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
765 HPT_U8 Description[64]; /* array description */
766 HPT_U8 CreateManager[16]; /* who created it */
769 HPT_U8 ArrayType; /* array type */
770 HPT_U8 BlockSizeShift; /* stripe size */
771 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
772 HPT_U8 SubArrayType;
783 HPT_U8 SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/
784 HPT_U8 reserved2[7];
801 HPT_U8 SasAddress[8];
808 HPT_U8 MaximumBlockTransfer;
809 HPT_U8 VendorUnique2;
813 HPT_U8 VendorUnique3;
814 HPT_U8 PioCycleTimingMode;
815 HPT_U8 VendorUnique4;
816 HPT_U8 DmaCycleTimingMode;
824 HPT_U8 SingleWordDMASupport;
825 HPT_U8 SingleWordDMAActive;
826 HPT_U8 MultiWordDMASupport;
827 HPT_U8 MultiWordDMAActive;
828 HPT_U8 AdvancedPIOModes;
829 HPT_U8 Reserved4;
843 * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
846 HPT_U8 ControllerId; /* controller id */
847 HPT_U8 PathId; /* bus */
848 HPT_U8 TargetId; /* id */
849 HPT_U8 DeviceModeSetting; /* Current Data Transfer mode: 0-4 PIO 0-4 */
851 HPT_U8 DeviceType; /* device type */
852 HPT_U8 UsableMode; /* highest usable mode */
855 HPT_U8 NCQEnabled: 1;
856 HPT_U8 NCQSupported: 1;
857 HPT_U8 TCQEnabled: 1;
858 HPT_U8 TCQSupported: 1;
859 HPT_U8 WriteCacheEnabled: 1;
860 HPT_U8 WriteCacheSupported: 1;
861 HPT_U8 ReadAheadEnabled: 1;
862 HPT_U8 ReadAheadSupported: 1;
863 HPT_U8 reserved6: 6;
864 HPT_U8 SpinUpMode: 2;
866 HPT_U8 ReadAheadSupported: 1;
867 HPT_U8 ReadAheadEnabled: 1;
868 HPT_U8 WriteCacheSupported: 1;
869 HPT_U8 WriteCacheEnabled: 1;
870 HPT_U8 TCQSupported: 1;
871 HPT_U8 TCQEnabled: 1;
872 HPT_U8 NCQSupported: 1;
873 HPT_U8 NCQEnabled: 1;
874 HPT_U8 SpinUpMode: 2;
875 HPT_U8 reserved6: 6;
889 * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
892 HPT_U8 ControllerId; /* controller id */
893 HPT_U8 PathId; /* bus */
894 HPT_U8 TargetId; /* id */
895 HPT_U8 DeviceModeSetting; /* Current Data Transfer mode: 0-4 PIO 0-4 */
897 HPT_U8 DeviceType; /* device type */
898 HPT_U8 UsableMode; /* highest usable mode */
901 HPT_U8 NCQEnabled: 1;
902 HPT_U8 NCQSupported: 1;
903 HPT_U8 TCQEnabled: 1;
904 HPT_U8 TCQSupported: 1;
905 HPT_U8 WriteCacheEnabled: 1;
906 HPT_U8 WriteCacheSupported: 1;
907 HPT_U8 ReadAheadEnabled: 1;
908 HPT_U8 ReadAheadSupported: 1;
909 HPT_U8 reserved6: 6;
910 HPT_U8 SpinUpMode: 2;
912 HPT_U8 ReadAheadSupported: 1;
913 HPT_U8 ReadAheadEnabled: 1;
914 HPT_U8 WriteCacheSupported: 1;
915 HPT_U8 WriteCacheEnabled: 1;
916 HPT_U8 TCQSupported: 1;
917 HPT_U8 TCQEnabled: 1;
918 HPT_U8 NCQSupported: 1;
919 HPT_U8 NCQEnabled: 1;
920 HPT_U8 SpinUpMode: 2;
921 HPT_U8 reserved6: 6;
977 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
978 HPT_U8 reserved[3];
992 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
993 HPT_U8 reserved[3];
1012 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
1013 HPT_U8 CachePolicy; /* refer to CACHE_POLICY_xxx */
1014 HPT_U8 VBusId; /* vbus sequence in vbus_list */
1015 HPT_U8 TargetId; /* OS target id. Value 0xFF is invalid */
1038 HPT_U8 revision;
1039 HPT_U8 reserved[7];
1041 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
1042 HPT_U8 CachePolicy; /* refer to CACHE_POLICY_xxx */
1043 HPT_U8 VBusId; /* vbus sequence in vbus_list */
1044 HPT_U8 TargetId; /* OS target id. Value 0xFF is invalid */
1088 HPT_U8 Name[MAX_ARRAYNAME_LEN]; /* array name */
1089 HPT_U8 Description[64]; /* array description */
1094 HPT_U8 DeviceModeSetting; /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
1099 HPT_U8 DeviceModeSetting; /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
1100 HPT_U8 TCQEnabled;
1101 HPT_U8 NCQEnabled;
1102 HPT_U8 WriteCacheEnabled;
1103 HPT_U8 ReadAheadEnabled;
1104 HPT_U8 SpinUpMode;
1105 HPT_U8 SetBadSector;
1106 HPT_U8 reserve[1];
1135 HPT_U8 target_type;
1136 HPT_U8 infor_type;
1138 #define SET_VDEV_INFO_param(p) ((HPT_U8 *)(p)+sizeof(SET_VDEV_INFO))
1139 /* HPT_U8 param[0]; */
1142 typedef HPT_U8 PARAM_ARRAY_NAME[MAX_ARRAYNAME_LEN] ;
1143 typedef HPT_U8 PARAM_ARRAY_DES[64];
1144 typedef HPT_U8 PARAM_DEVICE_MODE, PARAM_TCQ, PARAM_NCQ, PARAM_READ_AHEAD, PARAM_WRITE_CACHE, PARAM_CACHE_POLICY;
1153 HPT_U8 ArrayType; /* 1-level array type */
1154 HPT_U8 nDisk; /* number of elements in Members[] array */
1155 HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1156 HPT_U8 CreateFlags; /* See CAF_xxx */
1158 HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1159 HPT_U8 Description[64]; /* array description */
1160 HPT_U8 CreateManager[16]; /* who created it */
1169 HPT_U8 ArrayType; /* 1-level array type */
1170 HPT_U8 nDisk; /* number of elements in Members[] array */
1171 HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1172 HPT_U8 CreateFlags; /* See CAF_xxx */
1174 HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1175 HPT_U8 Description[64]; /* array description */
1176 HPT_U8 CreateManager[16]; /* who created it */
1188 HPT_U8 revision; /*CREATE_ARRAY_PARAMS_V3_REVISION*/
1189 HPT_U8 diskCachePolicy; /*unchange:0 enable:1 disable:2*/
1190 HPT_U8 reserved[4];
1191 HPT_U8 subDisks; /* RAIDn0 sub array */
1192 HPT_U8 SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/
1193 HPT_U8 ArrayType; /* 1-level array type */
1194 HPT_U8 nDisk; /* number of elements in Members[] array */
1195 HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1196 HPT_U8 CreateFlags; /* See CAF_xxx */
1198 HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1199 HPT_U8 Description[64]; /* array description */
1200 HPT_U8 CreateManager[16]; /* who created it */
1301 HPT_U8 EventType;
1302 HPT_U8 reserved[3];
1304 HPT_U8 Data[32]; /* various data depend on EventType */
1312 HPT_U8 bFeaturesReg; /* feature register */
1313 HPT_U8 bSectorCountReg; /* IDE sector count register. */
1314 HPT_U8 bLbaLowReg; /* IDE LBA low value. */
1315 HPT_U8 bLbaMidReg; /* IDE LBA mid register. */
1316 HPT_U8 bLbaHighReg; /* IDE LBA high value. */
1317 HPT_U8 bDriveHeadReg; /* IDE drive/head register. */
1318 HPT_U8 bCommandReg; /* Actual IDE command. Checked for validity by driver. */
1319 HPT_U8 nSectors; /* data size in sectors, if the command has data transfer */
1320 HPT_U8 protocol; /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
1321 HPT_U8 reserve[3];
1322 #define IDE_PASS_THROUGH_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER))
1323 /* HPT_U8 DataBuffer[0]; */
1334 HPT_U8 bDriveHeadReg; /* IDE drive/head register. */
1335 HPT_U8 bCommandReg; /* Actual IDE command. Checked for validity by driver. */
1337 HPT_U8 protocol; /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
1338 HPT_U8 reserve;
1339 #define IDE_PASS_THROUGH_V2_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER_V2))
1340 /* HPT_U8 DataBuffer[0]; */
1346 HPT_U8 protocol;
1347 HPT_U8 reserve1;
1348 HPT_U8 reserve2;
1349 HPT_U8 cdbLength;
1350 HPT_U8 cdb[16];
1357 HPT_U8 scsiStatus;
1358 HPT_U8 reserve1;
1359 HPT_U8 reserve2;
1360 HPT_U8 reserve3;
1373 HPT_U8 Command; /* IO_COMMAD_xxx */
1374 HPT_U8 BufferType; /* BUFFER_TYPE_xxx, see below */
1389 HPT_U8 value[32];
1390 HPT_U8 type; /* HPT_DRIVER_PARAMETER_TYPE_* */
1391 HPT_U8 persistent;
1392 HPT_U8 reserve2[2];
1393 HPT_U8 location; /* 0 - system */
1394 HPT_U8 controller;
1395 HPT_U8 bus;
1396 HPT_U8 reserve1;
1434 HPT_U8 sectors;
1435 HPT_U8 read;
1437 #define ACCESS_CONFIG_REG_buffer(p) ((HPT_U8 *)(p) + sizeof(ACCESS_CONFIG_REG_PARAMS))
1445 HPT_U8 sectors;
1446 HPT_U8 backsectors;
1447 HPT_U8 offset;
1448 HPT_U8 backoffset;
1724 int hpt_rebuild_data_block(DEVICEID idMirror, HPT_U32 Lba, HPT_U8 nSector);
1819 int hpt_lock_device(DEVICEID idDisk, HPT_U32 Lba, HPT_U8 nSectors);
1867 int hpt_verify_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
1879 int hpt_initialize_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
2139 int hpt_i2c_transaction(HPT_U8 *indata, HPT_U32 inlen, HPT_U8 *outdata, HPT_U32 outlen, HPT_U32 *poutlen);