Lines Matching defs:BUS_SPACE_WRT4_MVFREY2
183 #define BUS_SPACE_WRT4_MVFREY2(offset, value) bus_space_write_4(hba->bar2t,\
287 BUS_SPACE_WRT4_MVFREY2(f0_to_cpu_msg_a, msg);
773 BUS_SPACE_WRT4_MVFREY2(pcie_f0_int_enable, 0);
778 BUS_SPACE_WRT4_MVFREY2(f0_doorbell, status);
788 BUS_SPACE_WRT4_MVFREY2(isr_cause, status);
805 BUS_SPACE_WRT4_MVFREY2(pcie_f0_int_enable, 0x1010);
887 BUS_SPACE_WRT4_MVFREY2(inbound_write_ptr, hba->u.mvfrey.inlist_wptr);
1344 BUS_SPACE_WRT4_MVFREY2(inbound_write_ptr, hba->u.mvfrey.inlist_wptr);
1710 BUS_SPACE_WRT4_MVFREY2(inbound_base,
1712 BUS_SPACE_WRT4_MVFREY2(inbound_base_high,
1715 BUS_SPACE_WRT4_MVFREY2(outbound_base,
1717 BUS_SPACE_WRT4_MVFREY2(outbound_base_high,
1720 BUS_SPACE_WRT4_MVFREY2(outbound_shadow_base,
1722 BUS_SPACE_WRT4_MVFREY2(outbound_shadow_base_high,
2220 BUS_SPACE_WRT4_MVFREY2(f0_doorbell_enable, CPU_TO_F0_DRBL_MSG_A_BIT);
2223 BUS_SPACE_WRT4_MVFREY2(isr_enable, 0x1);
2226 BUS_SPACE_WRT4_MVFREY2(pcie_f0_int_enable, 0x1010);
2254 BUS_SPACE_WRT4_MVFREY2(f0_doorbell_enable, 0);
2257 BUS_SPACE_WRT4_MVFREY2(isr_enable, 0);
2260 BUS_SPACE_WRT4_MVFREY2(pcie_f0_int_enable, 0);
2631 BUS_SPACE_WRT4_MVFREY2(inbound_write_ptr, hba->u.mvfrey.inlist_wptr);