Lines Matching refs:HPT_U8
383 HPT_U8 MaximumControllers; /* maximum controllers the driver can support */
384 HPT_U8 SupportCrossControllerRAID; /* 1-support, 0-not support */
385 HPT_U8 MinimumBlockSizeShift; /* minimum block size shift */
386 HPT_U8 MaximumBlockSizeShift; /* maximum block size shift */
388 HPT_U8 SupportDiskModeSetting;
389 HPT_U8 SupportSparePool;
390 HPT_U8 MaximumArrayNameLength;
391 /* only one HPT_U8 left here! */
393 HPT_U8 reserved: 2;
394 HPT_U8 SupportPerformanceMonitor: 1;
395 HPT_U8 SupportVariableSectorSize: 1;
396 HPT_U8 SupportHotSwap: 1;
397 HPT_U8 HighPerformanceRAID1: 1;
398 HPT_U8 RebuildProcessInDriver: 1;
399 HPT_U8 SupportDedicatedSpare: 1;
401 HPT_U8 SupportDedicatedSpare: 1; /* call hpt_add_dedicated_spare() for dedicated spare. */
402 HPT_U8 RebuildProcessInDriver: 1; /* Windows only. used by mid layer for rebuild control. */
403 HPT_U8 HighPerformanceRAID1: 1;
404 HPT_U8 SupportHotSwap: 1;
405 HPT_U8 SupportVariableSectorSize: 1;
406 HPT_U8 SupportPerformanceMonitor: 1;
407 HPT_U8 reserved: 2;
411 HPT_U8 SupportedRAIDTypes[16];
413 HPT_U8 MaximumArrayMembers[16];
419 HPT_U8 SupportedCachePolicies[16];
431 HPT_U8 ChipType; /* chip type */
432 HPT_U8 InterruptLevel; /* IRQ level */
433 HPT_U8 NumBuses; /* bus count */
434 HPT_U8 ChipFlags;
436 HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
437 HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
443 HPT_U8 ChipType; /* chip type */
444 HPT_U8 InterruptLevel; /* IRQ level */
445 HPT_U8 NumBuses; /* bus count */
446 HPT_U8 ChipFlags;
448 HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
449 HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
453 HPT_U8 pci_tree;
454 HPT_U8 pci_bus;
455 HPT_U8 pci_device;
456 HPT_U8 pci_function;
462 HPT_U8 MaxWidth;
463 HPT_U8 CurrentWidth;
464 HPT_U8 MaxSpeed;
465 HPT_U8 CurrentSpeed;
466 HPT_U8 reserve[64];
498 HPT_U8 ChipType;
499 HPT_U8 InterruptLevel;
500 HPT_U8 NumBuses;
501 HPT_U8 ChipFlags;
502 HPT_U8 szProductID[MAX_NAME_LENGTH];
503 HPT_U8 szVendorID[MAX_NAME_LENGTH];
505 HPT_U8 pci_tree;
506 HPT_U8 pci_bus;
507 HPT_U8 pci_device;
508 HPT_U8 pci_function;
510 HPT_U8 IOPModel[32];
512 HPT_U8 BatteryInstalled;
513 HPT_U8 BatteryStatus;
517 HPT_U8 SerialNumber[32];
518 HPT_U8 BatteryMBInstalled;
519 HPT_U8 BatteryTemperature;
536 HPT_U8 SASAddress[8];
537 HPT_U8 reserve[48];
561 HPT_U8 EnclosureType;
562 HPT_U8 NumberOfPhys;
563 HPT_U8 AttachedTo;
564 HPT_U8 Status;
565 HPT_U8 VendorId[8];
566 HPT_U8 ProductId[16];
567 HPT_U8 ProductRevisionLevel[4];
574 HPT_U8 ElementType;
575 HPT_U8 ElementOverallIndex;
576 HPT_U8 ElementStatus;
577 HPT_U8 Reserved;
579 HPT_U8 ElementDescriptor[32];
623 HPT_U8 EnclosureType;
624 HPT_U8 NumberOfPhys;
625 HPT_U8 AttachedTo;
626 HPT_U8 Status;
627 HPT_U8 VendorId[8];
628 HPT_U8 ProductId[16];
629 HPT_U8 ProductRevisionLevel[4];
635 HPT_U8 EnclosureType;
636 HPT_U8 NumberOfPhys;
637 HPT_U8 AttachedTo;
638 HPT_U8 Status;
639 HPT_U8 VendorId[8];
640 HPT_U8 ProductId[16];
641 HPT_U8 ProductRevisionLevel[4];
649 HPT_U8 EnclosureType;
650 HPT_U8 NumberOfPhys;
651 HPT_U8 AttachedTo;
652 HPT_U8 Status;
653 HPT_U8 VendorId[8];
654 HPT_U8 ProductId[16];
655 HPT_U8 ProductRevisionLevel[4];
686 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
687 HPT_U8 Description[64]; /* array description */
688 HPT_U8 CreateManager[16]; /* who created it */
691 HPT_U8 ArrayType; /* array type */
692 HPT_U8 BlockSizeShift; /* stripe size */
693 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
694 HPT_U8 SubArrayType;
713 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
714 HPT_U8 Description[64]; /* array description */
715 HPT_U8 CreateManager[16]; /* who created it */
718 HPT_U8 ArrayType; /* array type */
719 HPT_U8 BlockSizeShift; /* stripe size */
720 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
721 HPT_U8 SubArrayType;
735 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
736 HPT_U8 Description[64]; /* array description */
737 HPT_U8 CreateManager[16]; /* who created it */
740 HPT_U8 ArrayType; /* array type */
741 HPT_U8 BlockSizeShift; /* stripe size */
742 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
743 HPT_U8 SubArrayType;
768 HPT_U8 Name[MAX_ARRAYNAME_LEN];/* array name */
769 HPT_U8 Description[64]; /* array description */
770 HPT_U8 CreateManager[16]; /* who created it */
773 HPT_U8 ArrayType; /* array type */
774 HPT_U8 BlockSizeShift; /* stripe size */
775 HPT_U8 nDisk; /* member count: Number of ID in Members[] */
776 HPT_U8 SubArrayType;
787 HPT_U8 SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/
788 HPT_U8 reserved2[7];
805 HPT_U8 SasAddress[8];
812 HPT_U8 MaximumBlockTransfer;
813 HPT_U8 VendorUnique2;
817 HPT_U8 VendorUnique3;
818 HPT_U8 PioCycleTimingMode;
819 HPT_U8 VendorUnique4;
820 HPT_U8 DmaCycleTimingMode;
828 HPT_U8 SingleWordDMASupport;
829 HPT_U8 SingleWordDMAActive;
830 HPT_U8 MultiWordDMASupport;
831 HPT_U8 MultiWordDMAActive;
832 HPT_U8 AdvancedPIOModes;
833 HPT_U8 Reserved4;
847 * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
850 HPT_U8 ControllerId; /* controller id */
851 HPT_U8 PathId; /* bus */
852 HPT_U8 TargetId; /* id */
853 HPT_U8 DeviceModeSetting; /* Current Data Transfer mode: 0-4 PIO 0-4 */
855 HPT_U8 DeviceType; /* device type */
856 HPT_U8 UsableMode; /* highest usable mode */
859 HPT_U8 NCQEnabled: 1;
860 HPT_U8 NCQSupported: 1;
861 HPT_U8 TCQEnabled: 1;
862 HPT_U8 TCQSupported: 1;
863 HPT_U8 WriteCacheEnabled: 1;
864 HPT_U8 WriteCacheSupported: 1;
865 HPT_U8 ReadAheadEnabled: 1;
866 HPT_U8 ReadAheadSupported: 1;
867 HPT_U8 reserved6: 6;
868 HPT_U8 SpinUpMode: 2;
870 HPT_U8 ReadAheadSupported: 1;
871 HPT_U8 ReadAheadEnabled: 1;
872 HPT_U8 WriteCacheSupported: 1;
873 HPT_U8 WriteCacheEnabled: 1;
874 HPT_U8 TCQSupported: 1;
875 HPT_U8 TCQEnabled: 1;
876 HPT_U8 NCQSupported: 1;
877 HPT_U8 NCQEnabled: 1;
878 HPT_U8 SpinUpMode: 2;
879 HPT_U8 reserved6: 6;
893 * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
896 HPT_U8 ControllerId; /* controller id */
897 HPT_U8 PathId; /* bus */
898 HPT_U8 TargetId; /* id */
899 HPT_U8 DeviceModeSetting; /* Current Data Transfer mode: 0-4 PIO 0-4 */
901 HPT_U8 DeviceType; /* device type */
902 HPT_U8 UsableMode; /* highest usable mode */
905 HPT_U8 NCQEnabled: 1;
906 HPT_U8 NCQSupported: 1;
907 HPT_U8 TCQEnabled: 1;
908 HPT_U8 TCQSupported: 1;
909 HPT_U8 WriteCacheEnabled: 1;
910 HPT_U8 WriteCacheSupported: 1;
911 HPT_U8 ReadAheadEnabled: 1;
912 HPT_U8 ReadAheadSupported: 1;
913 HPT_U8 reserved6: 6;
914 HPT_U8 SpinUpMode: 2;
916 HPT_U8 ReadAheadSupported: 1;
917 HPT_U8 ReadAheadEnabled: 1;
918 HPT_U8 WriteCacheSupported: 1;
919 HPT_U8 WriteCacheEnabled: 1;
920 HPT_U8 TCQSupported: 1;
921 HPT_U8 TCQEnabled: 1;
922 HPT_U8 NCQSupported: 1;
923 HPT_U8 NCQEnabled: 1;
924 HPT_U8 SpinUpMode: 2;
925 HPT_U8 reserved6: 6;
981 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
982 HPT_U8 reserved[3];
996 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
997 HPT_U8 reserved[3];
1016 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
1017 HPT_U8 CachePolicy; /* refer to CACHE_POLICY_xxx */
1018 HPT_U8 VBusId; /* vbus sequence in vbus_list */
1019 HPT_U8 TargetId; /* OS target id. Value 0xFF is invalid */
1042 HPT_U8 revision;
1043 HPT_U8 reserved[7];
1045 HPT_U8 Type; /* LDT_ARRAY or LDT_DEVICE */
1046 HPT_U8 CachePolicy; /* refer to CACHE_POLICY_xxx */
1047 HPT_U8 VBusId; /* vbus sequence in vbus_list */
1048 HPT_U8 TargetId; /* OS target id. Value 0xFF is invalid */
1092 HPT_U8 Name[MAX_ARRAYNAME_LEN]; /* array name */
1093 HPT_U8 Description[64]; /* array description */
1098 HPT_U8 DeviceModeSetting; /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
1103 HPT_U8 DeviceModeSetting; /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
1104 HPT_U8 TCQEnabled;
1105 HPT_U8 NCQEnabled;
1106 HPT_U8 WriteCacheEnabled;
1107 HPT_U8 ReadAheadEnabled;
1108 HPT_U8 SpinUpMode;
1109 HPT_U8 SetBadSector;
1110 HPT_U8 reserve[1];
1139 HPT_U8 target_type;
1140 HPT_U8 infor_type;
1142 #define SET_VDEV_INFO_param(p) ((HPT_U8 *)(p)+sizeof(SET_VDEV_INFO))
1143 /* HPT_U8 param[0]; */
1146 typedef HPT_U8 PARAM_ARRAY_NAME[MAX_ARRAYNAME_LEN] ;
1147 typedef HPT_U8 PARAM_ARRAY_DES[64];
1148 typedef HPT_U8 PARAM_DEVICE_MODE, PARAM_TCQ, PARAM_NCQ, PARAM_READ_AHEAD, PARAM_WRITE_CACHE, PARAM_CACHE_POLICY;
1157 HPT_U8 ArrayType; /* 1-level array type */
1158 HPT_U8 nDisk; /* number of elements in Members[] array */
1159 HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1160 HPT_U8 CreateFlags; /* See CAF_xxx */
1162 HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1163 HPT_U8 Description[64]; /* array description */
1164 HPT_U8 CreateManager[16]; /* who created it */
1173 HPT_U8 ArrayType; /* 1-level array type */
1174 HPT_U8 nDisk; /* number of elements in Members[] array */
1175 HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1176 HPT_U8 CreateFlags; /* See CAF_xxx */
1178 HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1179 HPT_U8 Description[64]; /* array description */
1180 HPT_U8 CreateManager[16]; /* who created it */
1192 HPT_U8 revision; /*CREATE_ARRAY_PARAMS_V3_REVISION*/
1193 HPT_U8 diskCachePolicy; /*unchange:0 enable:1 disable:2*/
1194 HPT_U8 reserved[4];
1195 HPT_U8 subDisks; /* RAIDn0 sub array */
1196 HPT_U8 SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/
1197 HPT_U8 ArrayType; /* 1-level array type */
1198 HPT_U8 nDisk; /* number of elements in Members[] array */
1199 HPT_U8 BlockSizeShift; /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1200 HPT_U8 CreateFlags; /* See CAF_xxx */
1202 HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1203 HPT_U8 Description[64]; /* array description */
1204 HPT_U8 CreateManager[16]; /* who created it */
1305 HPT_U8 EventType;
1306 HPT_U8 reserved[3];
1308 HPT_U8 Data[32]; /* various data depend on EventType */
1316 HPT_U8 bFeaturesReg; /* feature register */
1317 HPT_U8 bSectorCountReg; /* IDE sector count register. */
1318 HPT_U8 bLbaLowReg; /* IDE LBA low value. */
1319 HPT_U8 bLbaMidReg; /* IDE LBA mid register. */
1320 HPT_U8 bLbaHighReg; /* IDE LBA high value. */
1321 HPT_U8 bDriveHeadReg; /* IDE drive/head register. */
1322 HPT_U8 bCommandReg; /* Actual IDE command. Checked for validity by driver. */
1323 HPT_U8 nSectors; /* data size in sectors, if the command has data transfer */
1324 HPT_U8 protocol; /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
1325 HPT_U8 reserve[3];
1326 #define IDE_PASS_THROUGH_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER))
1327 /* HPT_U8 DataBuffer[0]; */
1338 HPT_U8 bDriveHeadReg; /* IDE drive/head register. */
1339 HPT_U8 bCommandReg; /* Actual IDE command. Checked for validity by driver. */
1341 HPT_U8 protocol; /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
1342 HPT_U8 reserve;
1343 #define IDE_PASS_THROUGH_V2_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER_V2))
1344 /* HPT_U8 DataBuffer[0]; */
1350 HPT_U8 protocol;
1351 HPT_U8 reserve1;
1352 HPT_U8 reserve2;
1353 HPT_U8 cdbLength;
1354 HPT_U8 cdb[16];
1361 HPT_U8 scsiStatus;
1362 HPT_U8 reserve1;
1363 HPT_U8 reserve2;
1364 HPT_U8 reserve3;
1377 HPT_U8 Command; /* IO_COMMAD_xxx */
1378 HPT_U8 BufferType; /* BUFFER_TYPE_xxx, see below */
1393 HPT_U8 value[32];
1394 HPT_U8 type; /* HPT_DRIVER_PARAMETER_TYPE_* */
1395 HPT_U8 persistent;
1396 HPT_U8 reserve2[2];
1397 HPT_U8 location; /* 0 - system */
1398 HPT_U8 controller;
1399 HPT_U8 bus;
1400 HPT_U8 reserve1;
1438 HPT_U8 sectors;
1439 HPT_U8 read;
1441 #define ACCESS_CONFIG_REG_buffer(p) ((HPT_U8 *)(p) + sizeof(ACCESS_CONFIG_REG_PARAMS))
1449 HPT_U8 sectors;
1450 HPT_U8 backsectors;
1451 HPT_U8 offset;
1452 HPT_U8 backoffset;
1728 int hpt_rebuild_data_block(DEVICEID idMirror, HPT_U32 Lba, HPT_U8 nSector);
1823 int hpt_lock_device(DEVICEID idDisk, HPT_U32 Lba, HPT_U8 nSectors);
1871 int hpt_verify_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
1883 int hpt_initialize_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
2143 int hpt_i2c_transaction(HPT_U8 *indata, HPT_U32 inlen, HPT_U8 *outdata, HPT_U32 outlen, HPT_U32 *poutlen);